AKD5354(2001) Ver la hoja de datos (PDF) - Asahi Kasei Microdevices
Número de pieza
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AKD5354 Datasheet PDF : 19 Pages
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ASAHI KASEI
[AK5354]
SWITCHING CHARACTERISTICS
(Ta=25°C; VA=2.1 ∼ 3.3V, VD=1.8 ∼ 3.3V; CL=20pF)
Parameter
Symbol
min
typ
Control Clock Frequency
Master Clock (MCLK) 256fs: Frequency
Pulse Width Low
Pulse Width High
fCLK
tCLKL
tCLKH
2.048
28
28
11.2896
384fs: Frequency
Pulse Width Low
Pulse Width High
fCLK
tCLKL
tCLKH
3.072
23
23
16.9344
Channel Clock (LRCK) Frequency
Duty Cycle
fs
8
44.1
45
Audio Interface Timing
BCLK Period
BCLK Pulse Width Low
Pulse Width High
BCLK “↓” to LRCK
LRCK Edge to SDTO (MSB)
BCLK “↓” to SDTO
tBLK
tBLKL
tBLKH
tBLR
tDLR
tDSS
312.5
130
130
-tBLKH+50
Control Interface Timing
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDATA Setup Time
CDATA Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
tCCK
200
tCCKL
80
tCCKH
80
tCDS
50
tCDH
50
tCSW
150
tCSS
50
tCSH
50
Reset / Calibration Timing
PDN Pulse Width
tPW
150
PDN “↑” to SDTO
(Note 7)
tPWV
4128
max
12.8
19.2
50
55
tBLKL-50
80
80
Units
MHz
ns
ns
MHz
ns
ns
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1/fs
Note: 7. These cycles are the numbers of LRCK rising from PDN pin rising.
MS0054-E-01
-6-
2001/01
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