AKD4383 Ver la hoja de datos (PDF) - Asahi Kasei Microdevices
Número de pieza
componentes Descripción
Fabricante
AKD4383 Datasheet PDF : 25 Pages
| |||
ASAHI KASEI
[AK4383]
D/A Converion Mode
OPERATION OVERVIEW
The AK4383 can perform D/A conversion for both PCM data and DSD data. When DSDM pin is “H”, DSD data can be
input from DCLK, DSDL and DSDR pins. PCM data can be input from BICK/DCLK, SDTI/DSDL and LRCK/DSDR
pins by setting DSDM pin to “L”. In this case, BICK/DCLK, SDTI/DSDL and LRCK/DSDR pins can accept DSD data by
enabling DSD mode via the register (D/P = “1”). When PCM/DSD mode changes by DSDM pin or D/P bit, the AK4383
should be reset by PDN pin or RSTN bit. (Refer to D/A conversion mode switching timing.)
DSDM pin
L
H
D/P bit
0
1
0
1
Pin 2-4
PCM
DSD
*
*
Pin 9-11
*
*
DSD
DSD
DAC Output
PCM
DSD
DSD
DSD
Table 1. DSD/PCM Mode Control(* Don’t care.)
System Clock
1) PCM Mode
The external clocks, which are required to operate the AK4383, are MCLK, LRCK and BICK. The master clock (MCLK)
should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation
filter and the delta-sigma modulator. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS =
“0”: Register 00H), the sampling speed is set by DFS0/1(Table 2). The frequency of MCLK at each sampling speed is set
automatically. (Table 3~5). In Auto Setting Mode (ACKS = “1”: Default), as MCLK frequency is detected automatically
(Table 6), and the internal master clock becomes the appropriate frequency (Table 7), it is not necessary to set DFS0/1.
All external clocks (MCLK, BICK and LRCK) should always be present whenever the AK4383 is in the normal operation
mode (PDN= ”H”). If these clocks are not provided, the AK4383 may draw excess current because the device utilizes
dynamic refreshed logic internally. The AK4383 should be reset by PDN= ”L” after threse clocks are provided. If the
external clocks are not present, the AK4383 should be in the power-down mode (PDN= ”L”). After exiting reset at
power-up etc., the AK4383 is in the power-down mode until MCLK is input.
DFS1
0
0
1
DFS0
0
1
0
Sampling Rate (fs)
Normal Speed Mode
8kHz~48kHz
Double Speed Mode
60kHz~96kHz
Quad Speed Mode
120kHz~192kHz
Default
Table 2. Sampling Speed (Manual Setting Mode)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
256fs
8.1920MHz
11.2896MHz
12.2880MHz
MCLK
384fs
512fs
12.2880MHz 16.3840MHz
16.9344MHz 22.5792MHz
18.4320MHz 24.5760MHz
768fs
24.5760MHz
33.8688MHz
36.8640MHz
BICK
64fs
2.0480MHz
2.8224MHz
3.0720MHz
Table 3. System Clock Example (Normal Speed Mode @Manual Setting Mode)
MS0090-E-00
- 10 -
2001/4
Share Link: 