AIT1042RS38P9 Ver la hoja de datos (PDF) - ANADIGICS
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AIT1042RS38P9 Datasheet PDF : 19 Pages
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AIT1042
Table 6: Digital 2-Wire Interface Specifications
(TC = +55 °C, VDD = +5.0 V, ref. Figure 3)
PARAMETER
SYMBOL
MIN
CLK Frequency
fCLK
1
Logic High Input (pins 23, 24)
VH
2.0
Logic Low Input (pins 23, 24)
VL
-
Logic Input Current Consumption (pins 23, 24)
ILOG
-
Address Select Input Current Consumtion (pin 25)
IAS
-
Data Sink Current (2)
IAK
-
Bus Free Time between a STOP and START
Condition
tBUF
1.3
Hold Time (repeated) START Condition. After this
period, the first clock pulse is generated.
tHD;STA
0.6
LOW period of CLK
tLOW
1.3
HIGH period of CLK
tHIGH
0.6
Set-up Time for a Repeated START Condition
tSU;STA
0.6
Data Hold Time (for 2-wire bus devices)
tHD;DAT
0.0
Data Set-up Time
tSU;DAT
100
Rise Time of DATA and CLK signals
tR
20 + 0.1Cb(1)
Fall Time of Data and CLK signals
tF
20 + 0.1Cb(1)
Set-up Time for STOP Condition
tSU;STO
0.6
Capacitive Load for Each Bus Line
Cb
-
Notes:
(1) Cb is the total capacitance of one bus line in pF.
(2) For maximum 0.8 V level during Acknowledge Pulse.
3. All timing values are referred to minimum VH and maximum VL levels.
MAX
400
-
0.8
10
10
4.0
-
-
-
-
-
0.9
-
300
300
-
400
UNIT
kHz
V
V
A
A
mA
s
s
s
s
s
s
ns
ns
ns
s
pF
DATA
tF
tLOW
tR
tSU;DAT
tF
tHD;STA
tSP
tR
tBUF
CLK
t t HD;STA
HD;DAT
tHIGH
tSU;STA
tSU;STO
S
Sr
P
S
Figure 3: Serial 2-Wire Data Input Timing
6
PRELIMINARY DATA SHEET - Rev 1.0
02/2009
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