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AIT1042

Integrated Digital Tuner with RF and IF Gain Control

ANADIGICS 

AIT1042

LOGIC PROGRAMMING

This section describes the programming interface for

the ANADIGICS AIT1042 integrated tuner.

PHYSICAL INTERFACE

Hosts that conform to the I2C-Bus Specification

standard can be used to program the AIT1042. The

physical layer interface is a two-wire serial bus using

CLOCK and DATA digital lines. The nominal bit rate of

the interface is 400 kbits/sec. For data transmission,

the signal on the DATA line must be stable when

the CLOCK signal is high, and the state of the data

must change only while the CLOCK signal is low. A

logic level transition on the DATA line during a high

CLOCK signal indicates the beginning or end of a data

transmission, as specified in the following sections and

shown in Figure 4.

Start

Indicator:

CLOCK

DATA

Table 7: Address Select Decoding

(VDD = +5 V)

Pin 25 VAS Voltage

Address (Hex)

1.1 to 1.7 V

C0

0 to 0.8 V

C2

2.1 to 2.7 V

C4

4.2 V to VDD

C6

Sending Data

If the received address byte matches the address set

by the VAS voltage, the AIT1042 will acknowledge by

pulling the data low before the 9th positive clock edge.

The host can then begin sending programming data in

8-bit words. The MSB is sent first and the LSB last.

The AIT1042 acknowledges receipt by pulling the

DATA line low for one clock pulse after each received

byte. The data acknowledgement tells the host it may

send the next data word. Each group of three data

words (24 bits total) is used to program one of seven

registers described below.

Stop

Indicator:

CLOCK

DATA

Figure 4: Transmission Indicators

Completing Data Transmission

After sending the final data word, the host sends a Stop

indicator to mark the end of data transmission. A Stop is

indicated by a low-to-high transition of the DATA signal

while the CLOCK signal is held high. After receiving

the Stop indicator, the AIT1042 ceases to send further

acknowledgements and begins to monitor the CLOCK

and DATA signals for the next Start indicator.

ADDRESSING THE AIT1042

The AIT1042 monitors the CLOCK and DATA signals

for a Start indication from the host. A Start is indicated

by a high-to-low transition of the DATA signal while the

CLOCK signal is high. Immediately following the Start

indicator, the host sends an 8-bit address word to the

AIT1042. Address words depend on the voltage on

Pin 25 (VAS), as shown in Table 7 (the MSB is sent

first, LSB last). Once the AIT1042 has recognized the

Start indicator and a valid address word, it sends an

address acknowledgement to the host by pulling the

DATA line low for one clock pulse. The host can then

begin to send data to program the AIT1042.

Note: The Stop indicator does not directly control when

the programming data is latched or takes effect; the

data takes effect immediately following the receipt of

each three-word block of data, which represents a

complete 24-bit divider register.

Re-sending Data

If, for some reason, the data transmission fails or is

interrupted, the host can resend the data. To resend

data, a new Start indicator and address word must be

sent prior to any data words.

PRELIMINARY DATA SHEET - Rev 1.0

11

02/2009

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