IDT7MP4045S15Z Ver la hoja de datos (PDF) - Integrated Device Technology
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IDT7MP4045S15Z Datasheet PDF : 8 Pages
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IDT7MP4045/7MP4145
256K x 32 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED) (1, 2, 3, 7)
tWC
ADDRESS
OE
CS
WE
DATA OUT
DATA IN
tAW
tAS
tWP (7)
tWR
tWHZ (6)
tOHZ (6)
(4)
tOW(6)
tDW
tDH
DATA VALID
tOHZ (6)
(4)
2703 drw 10
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED) (1, 2, 3, 5)
ADDRESS
CS
tAS
WE
DATAIN
tWC
tAW
tCW
tWR
tDW
tDH
DATA VALID
2703 drw 11
NOTES:
1. WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap (tWP) of a LOW CS and a LOW WE.
3. tWR is measured from the earlier of CS or WE going HIGH to the end of write cycle.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
6. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). This parameter is guaranteed by design, but not tested.
7. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data
to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified tWP.
15.2
6
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