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M95256-BN1

256/128 Kbit Serial SPI Bus EEPROM With High Speed Clock

STMicroelectronics 

Figure 3. Microcontroller and Memory Devices on the SPI Bus

SPI Interface with SDO

(CPOL, CPHA) = SDI

('0', '0') or ('1', '1') SCK

Master

(ST6, ST7, ST9,

ST10, Others)

CS3 CS2 CS1

CQD

M95xxx

S

CQD

M95xxx

S

M95256, M95128

CQD

M95xxx

S

AI01958C

SIGNAL DESCRIPTION

Serial Output (Q)

The output pin is used to transfer data serially out

of the Memory. Data is shifted out on the falling

edge of the serial clock.

Serial Input (D)

The input pin is used to transfer data serially into

the device. Instructions, addresses, and the data

to be written, are each received this way. Input is

latched on the rising edge of the serial clock.

Serial Clock (C)

The serial clock provides the timing for the serial

interface (as shown in Figure 4). Instructions,

addresses, or data are latched, from the input pin,

on the rising edge of the clock input. The output

data on the Q pin changes state after the falling

edge of the clock input.

Chip Select (S)

When S is high, the memory device is deselected,

and the Q output pin is held in its high impedance

state. Unless an internal write operation is

underway, the memory device is placed in its

stand-by power mode.

After power-on, a high-to-low transition on S is

required prior to the start of any operation.

Write Protect (W)

The protection features of the memory device are

summarized in Table 3.

The hardware write protection, controlled by the W

pin, restricts write access to the Status Register

(though not to the WIP and WEL bits, which are

set or reset by the device internal logic).

Bit 7 of the status register (as shown in Table 5) is

the Status Register Write Disable bit (SRWD).

When this is set to 0 (its initial delivery state) it is

possible to write to the status register if the WEL

bit (Write Enable Latch) has been set by the

WREN instruction (irrespective of the level being

applied to the W input).

When bit 7 (SRWD) of the status register is set to

1, the ability to write to the status register depends

on the logic level being presented at pin W:

– If W pin is high, it is possible to write to the

status register, after having set the WEL bit

using the WREN instruction (Write Enable

Latch).

– If W pin is low, any attempt to modify the status

register is ignored by the device, even if the

WEL bit has been set. As a consequence, all the

data bytes in the EEPROM area, protected by

the BPn bits of the status register, are also

hardware protected against data corruption,

and appear as a Read Only EEPROM area for

the microcontroller. This mode is called the

Hardware Protected Mode (HPM).

It is possible to enter the Hardware Protected

Mode (HPM) either by setting the SRWD bit after

pulling low the W pin, or by pulling low the W pin

after setting the SRWD bit.

The only way to abort the Hardware Protected

Mode, once entered, is to pull high the W pin.

If W pin is permanently tied to the high level, the

Hardware Protected Mode is never activated, and

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