AIC1533 Ver la hoja de datos (PDF) - Analog Intergrations
Número de pieza
componentes Descripción
Fabricante
AIC1533 Datasheet PDF : 17 Pages
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AIC1533
During off state, Q2 at on stage and Q3 off stage,
voltage of C2 is the addition of VCC and VCFLY1.
And then go back to on state with voltage of CFLY2
equal to VC2, which is twice as much voltage as
VCC. Lastly, the system goes to off state, voltage of
Co1 is the addition of VCC and CFLY2, that is, three
times as much voltage as VCC.
Fig.17 shows the structure of a negative charge
pump. During on state, which represents Q4 at on
stage and Q5 at off stage, voltage of CFLY3 is equal
to VCC. During off state, indicating Q4 at off stage
and Q5 on stage, SWN pin connects to PGND
directly, and voltage of Co2 equals to -VCC.
12VIN
AIC1533
VCC
Q1
C1
C2
D1
1
3
2
SUPP
CFLY1 SWP
FBP
D2
1
CFLY2
3
2
Q2
Q3
PGND
Vp
+
Co1
-
R1
R2
C3
Fig.16 Structure of Positive Charge Pump
AIC1533
VCC
SWN
Q4 CFLY3
3
Q5 FBN
D3
1
2
VREF
PGND
Vn
-
R5 C5
Co2
+
R6
C4
Fig. 17 Structure of Negative Charge Pump
Power-Up Sequence And Adjustable Delay
Time
For thin-film transistor (TFT) liquid crystal display
applications, power-up sequence of three output
voltages is required. Fig. 3 indicates the power-up
sequence of AIC1533. After shutdown exit delay
time, output of LDO starts rising. When it reaches to
90% of normal voltage, which is determined by an
external resistor divider, CN starts being charged
from 5µA current source (referring to BLOCK
DIAGRAM). The charging time of CN, defined as T1,
can be calculated as
T1 = Cn × VTH,n
(1)
In
where VTH,η = negative threshold voltage, 1.25V,
In = negative bias current, 5µA
Afterwards, while negative output voltage starts
decreasing from 0V, VFBN decreases from 1.1V to
0V proportionally. As VFBN decreases to 10% of
VREF, Q7 turns off and Cp starts being charged
from 5µA current source (referring to BLOCK
DIAGRAM). The charging time of CP, defined as T2,
can be calculated as
11
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