AHA4013B-050 Ver la hoja de datos (PDF) - Unspecified

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AHA4013B-050

12.5 MBytes/sec Reed-Solomon Error Correction Device

Unspecified 

Advanced Hardware Architectures, Inc.

2.3 SIGNAL DESCRIPTIONS

Input Pins

DI[7:0] Data Input Bus. The input byte and ERASE

are latched on the rising edge of the clock

when both DSIN and RDYIN are active. If

either DSIN or RDYIN are inactive, the DI

and ERASE are ignored.

DSIN Data Input Strobe. Enables data from DI to

be loaded into the chip. When RDYIN is

active, DSIN being active on the rising

edge of the clock loads the input data in the

device. DSIN must be active for one clock

edge only per each input byte. DSIN is

ignored if RDYIN is inactive. Signal is

active low.

DSON Data Output Strobe. This input strobe

acknowledges to the chip that data

available on the Output Bus, DO, has been

received by the system. The device uses

this strobe to increment its internal address

counter to the next data location. DSON

must be active for one clock edge only per

each output byte. DSON is ignored if

RDYON is inactive. Active low.

ERASE Erasure input flag for symbol currently on

DI. Signal is active high. ERASE signal is

used for marking all check Bytes as

erasures (dummy check Bytes) during

encode operation. It is also used to mark

input symbols that contain errors during

decoding. If not used, connect this signal to

ground.

RSTN Reset. Input pin. When RSTN is active and

DSIN and DSON are inactive, the device

forces all internal control circuitry into a

known state and initializes all data path

elements. RSTN is active during

Initialization Phase. In this phase, internal

registers are programmed by using DI and

DSIN. Signal is active low.

CLK Clock. System clock input. Refer to

Section 4.4 AC Electrical Characteristics

for clock requirements.

Output Pins

RDYIN Ready Input. Indicates the chip’s ability to

accept data input on DI. If active, DSIN is

allowed to enable the loading of input data

on DI. When inactive, DSIN is ignored.

Signal is active low.

DO[7:0] Data Output. The output byte is available

on this bus. The value of the output byte is

undefined if RDYON is inactive. Requires

an acknowledge strobe, DSON, at a rising

edge of the clock to increment internal

address counter and output the next

location in the buffer. DO bus is always

driven and is not tristated by the device.

RDYON Ready Output. This output pin indicates the

chip’s ability to generate output data. If

active, DSON is allowed to increment the

internal address counter for the next data

byte. When inactive DSON is ignored and

DO is undefined. Signal is active low.

CRTN Correctable. The output pin when active

indicates the block did not exceed the error

threshold programmed by P. Error

threshold must be programmed with the

same value as the number of check symbols

R if erasures are not used. This signal is

valid when the first message byte, XK−1, of

the block is available out of the chip.

During all other times the signal is

undefined. Signal is valid for at least one

clock. Active low.

ERR Error. Output pin indicates the current

value on DO[7:0] is a corrected byte.

Active high.

2.4 PINOUT

INPUT

VDD 7

39 VDD

GND 8

38 VDD

VDD 9 AHA4013B-050 PJC 37 GND

GND 10

36 VDD

GND 11

35 RSTN

VDD 12

34 ERASE

*NC 13

33 DSON

*NC 14

32 RDYIN

VDD 15

31 RDYON

GND 16

30 GND

GND 17

29 GND

Page 4 of 24

OUTPUT

*NC = No connect, reserved for future considerations.

PS4013B-0600

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