AFBR-5805AZ Ver la hoja de datos (PDF) - Avago Technologies

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AFBR-5805AZ

ATM Transceivers for SONET OC-3 / SDH STM-1 in Low Cost 1 x 9 Package Style

Avago Technologies 

Recommended Handling Precautions

Avago Technologies recommends that normal static pre-

cautions be taken in the handling and assembly of these

transceivers to prevent damage which may be induced

by electrostatic discharge (ESD). The AFBR-5800Z series

of transceivers meet MIL-STD-883C Method 3015.4 Class

2 products.

Care should be used to avoid shorting the receiver data or

signal detect outputs directly to ground without proper

current limiting impedance.

Solder and Wash Process Compatibility

The transceivers are delivered with protective process

plugs inserted into the duplex SC or duplex ST connector

receptacle. This process plug protects the optical subas-

semblies during wave solder and aqueous wash process-

ing and acts as a dust cover during shipping.

These transceivers are compatible with either industry

standard wave or hand solder processes.

Shipping Container

The transceiver is packaged in a shipping container de-

signed to protect it from mechanical and ESD damage

during shipment or storage.

Board Layout - Decoupling Circuit and Ground Planes

It is important to take care in the layout of your circuit

board to achieve optimum performance from these trans-

ceivers. Figure 7 provides a good example of a schematic

for a power supply decoupling circuit that works well

with these parts. It is further recommended that a con-

tiguous ground plane be provided in the circuit board di-

rectly under the transceiver to provide a low inductance

ground for signal return current. This recommendation is

in keeping with good high frequency board layout prac-

tices.

Rx

;;;;

NO INTERNAL CONNECTION

Tx

;;;;;;

NO INTERNAL CONNECTION

AFBR-5805Z

TOP VIEW

Rx

Rx Tx

Tx

VEE

RD RD

SD

VCC

VCC

TD

TD VEE

;;;;1 ;;;;2 ;; ;;3;; ;;4;; ;;;;5 ;; ;;6;; ;;7;; ;;;;8 ;;;;9 ;;

C1

C2

TERMINATION

AT PHY

DEVICE

INPUTS

VCC

R5 R7

C6

R6

R8

L1 L2

C3

C4

VCC FILTER

AT VCC PINS

TRANSCEIVER

R9

R10

;;;RD;;; ;;;R;;;D;;; ;;;S;;;D ;;;VC;;;C

VCC

R2 R3

R1

R4

C5

TERMINATION

AT TRANSCEIVER

INPUTS

;;;T;;;D

;;;TD;;;

NOTES:

THE SPLIT-LOAD TERMINATIONS FOR ECL SIGNALS NEED TO BE LOCATED AT THE INPUT

OF DEVICES RECEIVING THOSE ECL SIGNALS. RECOMMEND 4-LAYER PRINTED CIRCUIT

BOARD WITH 50 OHM MICROSTRIP SIGNAL PATHS BE USED.

R1 = R4 = R6 = R8 = R10 = 130 OHMS FOR +5.0 V OPERATION, 82 OHMS FOR +3.3 V OPERATION.

R2 = R3 = R5 = R7 = R9 = 82 OHMS FOR +5.0 V OPERATION, 130 OHMS FOR +3.3 V OPERATION.

C1 = C2 = C3 = C5 = C6 = 0.1 µF.

C4 = 10 µF.

L1 = L2 = 1 µH COIL OR FERRITE INDUCTOR.

Figure 7. Recommended Decoupling and Termination Circuits

7

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