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HV9606SP

Current-Mode PWM Controller with Supervisor

Supertex Inc 

Functional Description – Continued

Start-Up Regulator

The start-up regulator guarantees a maximum VIN pin leakage

current of 6µA at 20V at the VIN pin while it is inhibited by the

START/STOP circuit. When the effective input voltage exceeds

the programmed START voltage, the regulator is turned on and

seeks to provide a nominal 2.9V at the VDD pin, which is the supply

voltage for all internal circuitry within the HV9606 except the

start/stop circuit. This regulator is capable of input voltages up to

250 Volts, which is the typical maximum arrester voltage limit used

to provide protection on telephone wires. Due to the high voltage

rating of the regulator the HV9606 can be used for applications

operating from rectified AC mains up to 140Vrms. The regulator

can supply a minimum of 5mA, which is sufficient to power the

internal circuitry and provide gate drive power for the external

MOSFET until the bootstrap circuit from the output of the PWM

drives the voltage on the VDD pin higher than the regulator set

point. This forces the regulator to turn off and reduce the input

current at the Vin pin to leakage levels. The VDD pin is typically

bypassed with a capacitor of at least 1µF, which provides the peak

currents required by the voltage doubler and in turn the gate driver

for the external MOSFET.

For low power applications the circuit may be operated without

bootstrapping. Care should be taken to assure that the power

dissipation in the regulator does not become excessive, as it might

be if the input voltage is high and the gate drive energy required is

high (operating at high frequency).

Low voltage operation of the HV9606 is also possible by powering

VDD from supply voltages of 2.9V to 5.5V. In these applications the

Vin, START and STOP pins should be connected to SGND pin.

When powering only via VDD, the START/STOP control is not

available and the startup regulator circuit is not used.

VDD Under Voltage Lockout

To guarantee correct operation, internal circuitry is held reset by an

under voltage lockout (VDD UVLO) until the regulator output voltage

is at least 100mV below the startup regulator set point. To

guarantee stable starting the VDD UVLO has a hysteresis of

100mV.

Oscillator

The oscillator circuit operates at twice the PWM output frequency.

The frequency can be programmed in the range of 30kHz to

800kHz by means of a single resistor connected from the RT pin to

SGND. For a given frequency the value of the resistor can be

calculated using the following equation:

RT = [(1 / fOSC) –1x10-7] / 42.6x10-12

HV9606

Synchronization

The SYNC pin is an input/output (I/O) port to a unique fault tolerant

peer-to-peer and/or to master clock synchronization circuit. For

synchronization the SYNC pins of multiple HV9606 based

converters can be connected together and may also be connected

to the open drain/collector output of an external master clock.

When connected in this manner the oscillators will lock to the

device with the highest operating frequency. The LOW duty cycle

of an external master clock should not exceed 50%. When

synchronized in this manner, a permanent logic HIGH or LOW

condition on the SYNC pin will result in a loss of synchronization,

but the HV9606 based converters will continue to operate at their

individually set operating frequency. For this reason the SYNC pin

is considered fault tolerant, since loss of synchronization will not

result in total system failure.

Depending on the cumulative parasitic capacitance on the SYNC

pin when connected in the above manner a pull up resistor may be

required from the SYNC pin to the VDD pin on each HV9606 based

DC/DC converter circuit. The value of the resistor will depend on

the cumulative parasitic capacitance and operating frequency.

Voltage Doubler

The HV9606 can operate on internal voltages ranging from 2.9V to

5.5V. It may be difficult to find power MOSFETs capable of

operating with such low gate drive voltages. For this reason the

HV9606 incorporates a voltage doubler circuit that generates a

voltage on the VX2 pin that is approximately two times the VDD

voltage. This circuit uses capacitive charge transfer methods and

requires the connection of a capacitor (typically 0.01µF) between

the CA and CB pins as well as an energy storage capacitor

(typically 0.1µF) connected from the VX2 pin to PGND pin. The

voltage doubler operates at the PWM output frequency.

The gate driver output on the GATE pin operates from the VX2

voltage, logic level (5Volt) gate power MOSFETs may be used

when VDD is bootstrapped at 3.3V or standard (10V) gate

MOSFETs may be used when VDD is bootstrapped at 5V.

VX2 Under Voltage Lockout

To guarantee that sufficient gate drive voltage is available, an

under voltage lockout circuit (VX2 UVLO) monitors the VX2

voltage. If the VX2 voltage drops below 4.5V the gate driver output

of the PWM circuit is inhibited to prevent damage to the power

MOSFET. This under voltage lockout has a hysteresis of 400mV

to prevent spurious operation.

Band Gap Reference

The operating limits of all internal circuits, except the

START/STOP circuit, are based on the !1% tolerance band gap

reference voltage available on the REF pin. It is capable of

delivering 100µA for use by external circuitry without degrading the

reference. A bypass capacitor of at least 0.1µF should be

connected from the REF pin to SGND pin.

6

4/15/2002-R.L2

Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com

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