ADV7623BSTZ Ver la hoja de datos (PDF) - Analog Devices
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ADV7623BSTZ Datasheet PDF : 16 Pages
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Data Sheet
ADV7623
Pin No. Mnemonic Type
56
TX2−
HDMI output
57
TX2+
HDMI output
58
TXGND
Ground
59
CEC
Digital I/O
60
DGND
Ground
61
DVDD
Power
62
ALSB
Digital input
63
CS
Digital input
64
EP_SCK
Digital output
65
EP_CS
Digital output
66
EP_MOSI
Digital output
67
EP_MISO
Digital input
68
MCLK_IN
Digital input
69
SCLK_IN
Digital input
70
AP5_IN
Digital input
71
AP4_IN
Digital input
72
DGNDIO
Ground
73
DVDDIO
Power
74
AP3_IN
Digital input
75
AP2_IN
Digital input
76
AP1_IN
Digital input
77
AP0_IN
Digital input
78
SDATA
Digital I/O
79
SCL
Digital input
80
DGND
Ground
81
DVDD
Power
82
INT1
Digital output
(AMUTE1)
83
INT2
Digital output
(AMUTE2)
84
INT_TX
Digital output
85
DGNDIO
Ground
86
DVDDIO
Power
87
AP0_OUT Digital output
88
AP1_OUT Digital output
89
AP2_OUT Digital output
90
AP3_OUT Digital output
91
AP4_OUT Digital output
92
DGND
Ground
93
DVDD
Power
94
AP5_OUT Digital output
95
SCLK_OUT Digital output
96
MCLK_OUT Digital output
97
RESET
Digital input
98
PWRDN
Digital input
Description
Differential Output Channel 2 Complement. Differential output of the red data at 10×
the pixel clock rate; supports TMDS logic level.
Differential Output Channel 2 True. Differential output of the red data at 10× the pixel
clock rate; supports TMDS logic level.
TXAVDD Ground.
Consumer Electronics Control Channel (5 V Tolerant).
DVDD Ground.
Digital Supply Voltage (1.8 V).
This pin is used to set the I2C address of the Rx IO and the Tx main map.
Chip Select Pin. This pin must be set low or left floating for the chip to process I2C messages
that are destined for the ADV7623. The ADV7623 ignores I2C messages that it receives if
this pin is high.
SPI Clock Interface for the EDID/OSD.
SPI Chip Selected Interface for the EDID/OSD.
SPI Master Out/Slave In for the EDID/OSD.
SPI Master In/Slave Out for the EDID/OSD.
Audio Reference Clock. 128 × N × fS with N = 1, 2, 3, or 4. Set to 128 × sampling frequency (fS),
256 × fS, 384 × fS, or 512 × fS. It supports CMOS logic levels from 1.8 V to 3.3 V.
I2S Audio Clock. It supports CMOS logic levels from 1.8 V to 3.3 V.
Audio Input Port 5. It supports CMOS logic levels from 1.8 V to 3.3 V.
Audio Input Port 4. It supports CMOS logic levels from 1.8 V to 3.3 V.
DVDDIO Ground.
Digital I/O Supply Voltage (3.3 V).
Audio Input Port 3. It supports CMOS logic levels from 1.8 V to 3.3 V.
Audio Input Port 2. It supports CMOS logic levels from 1.8 V to 3.3 V.
Audio Input Port 1. It supports CMOS logic levels from 1.8 V to 3.3 V.
Audio Input Port 0. It supports CMOS logic levels from 1.8 V to 3.3 V.
I2C Port Serial Data Input/Output Pin. SDATA is the data line for the control port.
I2C Port Serial Clock Input. SCL is the clock line for the control port.
DVDD Ground.
Digital Supply Voltage (1.8 V).
Interrupt Pin. This pin can be active low or active high. When status bits change, this pin is
triggered. The events that trigger an interrupt are under user control. This pin can also output
an audio mute signal.
Interrupt Pin. This pin can be active low or active high. When status bits change, this pin is
triggered. The events that trigger an interrupt are under user control. This pin can also output
an audio mute signal.
Interrupt; Open Drain. A 2 kΩ pull-up resistor to the microcontroller I/O supply is recommended.
DVDDIO Ground.
Digital I/O Supply Voltage (3.3 V).
Audio Output Port 0.
Audio Output Port 1.
Audio Output Port 2.
Audio Output Port 3.
Audio Output Port 4.
DVDD Ground.
Digital Supply Voltage (1.8 V).
Audio Output Port 5.
Audio Serial Clock Output.
Audio Master Clock Output.
System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset
the ADV7623 circuitry.
Active Low Power-Down Pin. If used, this pin should be pulled high to power up the
ADV7623. This pin can also be used as an in system power detect where internal EDID can
be powered from a 5 V signal of the HDMI port when it is connected to active equipment.
Rev. D | Page 11 of 16
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