ADV7511WBSWZ-RL Ver la hoja de datos (PDF) - Analog Devices
Número de pieza
componentes Descripción
Fabricante
ADV7511WBSWZ-RL Datasheet PDF : 12 Pages
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ADV7511W
Parameter
AUDIO AC TIMING
SCLK Duty Cycle
When N/2 Is an Even Number
When N/2 Is an Odd Number
I2S[3:0], SPDIF Setup Time (tASU)
I2S[3:0], SPDIF Hold Time (tAHLD)
LRCLK Setup Time (tASU)
LRCLK Hold Time (tAHLD)
CEC
CEC_CLK Frequency
CEC_CLK Accuracy
I2C INTERFACE
SCL Clock Frequency
SDA Setup Time (tDSU)
SDA Hold Time (tDHO)
Setup for Start (tSTASU)
Hold Time for Start (tSTAH)
Setup for Stop (tSTOSU)
Test Conditions/
Comments
Test
Temp Level1 Min Typ
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
IV
Full
VIII
Full
VIII
Full
Full
Full
Full
Full
Full
40
50
49
50
2
2
2
2
3
12 4
−2
100
100
0.6
0.6
0.6
1 See the Explanation of Test Levels section.
2 This is measured at 0.9 V. The relationship between clock and data is programmable in 400 ps steps.
3 UI is the unit interval.
4 12 MHz crystal oscillator for default register settings.
Max
60
51
100
+2
400
Unit
%
%
ns
ns
ns
ns
MHz
%
kHz
ns
ns
μs
μs
μs
Rev. 0 | Page 4 of 12
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