ADV7322(RevPrA) Ver la hoja de datos (PDF) - Analog Devices
Número de pieza
componentes Descripción
Fabricante
ADV7322 Datasheet PDF : 88 Pages
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ADV7322
Preliminary Technical Data
TIMING SPECIFICATIONS
VAA = 2.375 V − 2.625 V, VDD = 2.375 V − 2.625 V, VDD_IO = 2.375 V − 3.6 V, VREF = 1.235 V, RSET = 3040 Ω, RLOAD = 300 Ω. All specifications
TMIN to TMAX (0°C to 70°C), unless otherwise noted.
Table 4.
Parameter
MPU PORT1
SCLOCK Frequency
SCLOCK High Pulse Width, t1
SCLOCK Low Pulse Width, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
SDATA, SCLOCK Rise Time, t6
SDATA, SCLOCK Fall Time, t7
Setup Time (Stop Condition), t8
RESET Low Time
ANALOG OUTPUTS
Analog Output Delay2
Output Skew
CLOCK CONTROL AND PIXEL PORT3
fCLK
fCLK
Clock High Time, t9
Clock Low Time, t10
Data Setup Time, t111
Data Hold Time, t121
SD Output Access Time, t13
SD Output Hold Time, t14
HD Output Access Time, t13
HD Output Hold Time, t14
PIPELINE DELAY4
Min Typ Max Unit
Test Conditions
0
400 kHz
0.6
µs
1.3
µs
0.6
µs
0.6
µs
100
ns
300 ns
300 ns
0.6
µs
100
ns
First clock generated after this period relevant
for repeated start condition
7
ns
1
ns
29.5 MHz
SD PAL square pixel mode
81
MHz
PS/HD async mode
40
% of one clk cycle
40
% of one clk cycle
2.0
ns
2.0
ns
15 ns
5.0
ns
14 ns
5.0
ns
63
clk cycles
SD [2×, 16×]
76
clk cycles
SD component mode [16×]
35
clk cycles
PS [1×]
41
clk cycles
PS [8×]
36
clk cycles
HD [2×, 1×]
1 Guaranteed by characterization.
2Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition.
3Data: C[9:0]; Y[9:0], S[9:0]
Control: P_HSYNC, P_VSYNC, P_BLANK, S_HSYNC, S_VSYNC, S_BLANK
4SD, PS = 27 MHz, HD = 74.25 MHz.
Rev. PrA | Page 8 of 88
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