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ADV7152LS170

CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC

Analog Devices 

ADV7152

Mnemonic

Function

R/W

Read/Write Control (TTL Compatible Input). This input determines whether data is

written to or read from the device’s registers and color palette RAM. R/W and CE must

be at Logic “0” to write data to the part. R/W must be at Logic “1” and CE at Logic

“0” to read from the device.

C0, C1

Command Controls (TTL Compatible Inputs). These inputs determine the type of read

or write operation being performed on the device over the databus (see Interface Truth

Table). Data on these inputs is latched on the falling edge of CE.

IOR; IOR, IOG; IOG, IOB;

IOB

Red, Green and Blue Current Outputs (High Impedance Current Sources). These RGB

video outputs are specified to directly drive RS-343A and RS-170 video levels into dou-

bly terminated 75 Ω loads.

OBSOLETE VREF

RSET

IOR, IOG and IOB are the complementary outputs of IOR, IOG and IOB. These out-

puts can be tied to GND if it is not required to use differential outputs.

Voltage Reference Input (Analog Input). An external 1.235 V voltage reference is re-

quired to drive this input. An AD589 (2-terminal voltage reference) or equivalent is rec-

ommended. (Note: It is not recommended to use a resistor network to generate the

voltage reference.)

Output Full-Scale Adjust Control (Analog Input). A resistor connected between this pin

and analog ground controls the absolute amplitude of the output video signal. The value

of RSET is derived from the full-scale output current on IOG according to the following

equations:

RSET (Ω) = C1 × RREF/IOG (mA); SYNC on GREEN

RSET (Ω) = C2 × RREF/IOG (mA); No SYNC on GREEN.

Full-Scale output currents on IOR and IOB for a particular value of RSET are given by:

IOR (mA)= C2 × RREF(V)/RSET (Ω)

and

IOB (mA) = C2 × RREF (V)/RSET (Ω)

where C1 = 6,050: PEDESTAL = 7.5 IRE

where C1 = 5,723: PEDESTAL = 0 IRE

and

where C2 = 4,323: PEDESTAL = 7.5 IRE

where C1 = 3,996: PEDESTAL = 0 IRE.

COMP

Compensation Pin. A 0.1 µF capacitor should be connected between this pin and VAA.

IPLL

Phase Lock Loop Output Current (High Impedance Current Source). This output is

used to enable multiple ADV7150/ADV7152s along with ADV7151s to be synchronized

together with subpixel resolution when using an external PLL. This output is triggered

either from the falling edge of SYNC or BLANK as determined by bit CR21 of Com-

mand Register 2. When activated, it supplies a current corresponding to

IPLL (mA) = 1,728 × RREF(V)/RSET (Ω)

When not using the IPLL function, this output pin should be tied to GND.

VAA

Power Supply (+5 V ± 5%). The part contains multiple power supply pins, all should be

connected together to one common +5 V filtered analog power supply.

GND

Analog Ground. The part contains multiple ground pins, all should be connected

together to the system’s ground plane.

REV. B

–9–

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