ADT7483A(2012) Ver la hoja de datos (PDF) - ON Semiconductor

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ADT7483A
(Rev.:2012)

Dual Channel Temperature Sensor and Over Temperature Alarm

ON Semiconductor 

ADT7483A

Table 5. ELECTRICAL CHARACTERISTICS (TA = −40C to +125C, VDD = 3 V to 3.6 V, unless otherwise noted) (Note 1)

Parameter

Test Conditions

Min Typ Max Unit

Power Supply

Supply Voltage, VDD

Average Operating Supply Current, IDD

0.0625 Conversions/sec Rate (Note 1)

Standby Mode

3.0

3.3

3.6

V

−

240

350

mA

−

5

30

Undervoltage Lockout Threshold

Power-On-Reset Threshold

Temperature-to-Digital Converter (Note 2)

Local Sensor Accuracy

Resolution

Remote Diode Sensor Accuracy

Resolution

Remote Sensor Source Current (Note 3)

VDD Input, Disables ADC, Rising Edge

−

2.55

−

V

1

−

2.5

V

0C  TA  70C

0C  TA  85C

−40C  TA  +100C

−

−

1

C

−

−

1.5

−

−

2.5

−

1

−

0C  TA  70C, −55C  TD  150C (Note 3)

−

0C  TA  85C, −55C  TD  150C (Note 3)

−

−40C  TA  +125C, −55C  TD  150C

−

(Note 3)

−

1

C

−

1.5

−

2.5

−

0.25

−

High Level

Low Level

−

233

−

mA

−

14

−

Conversion Time

from Stop Bit to Conversion Complete

−

(All Channels), One-shot Mode with Averaging

Switched On

One-shot Mode with Averaging Off,

−

(Conversion Rate = 16, 32, or 64

Conversions/sec)

73

94

ms

11

14

Open-drain Digital Outputs (THERM, ALERT/THERM2)

Output Low Voltage, VOL

High Level Output Current, IOH

SMBus Interface (Notes 3 and 4)

IOUT = −6.0 mA

VOUT = VDD

−

−

0.4

V

−

0.1

1

mA

Logic Input High Voltage, VIH, SCLK, SDATA

Logic Input Low Voltage, VIL, SCLK, SDATA

Hysteresis

2.1

−

−

V

−

−

0.8

V

−

500

−

mV

SDA Output Low Voltage, VOL

Logic Input Current, IIH, IIL

SMBus Input Capacitance, SCLK, SDATA

IOUT = −6.0 mA

−

−

0.4

V

−1

−

+1

mA

−

5

−

pF

SMBus Clock Frequency

−

−

400 kHz

SMBus Timeout (Note 5)

User Programmable

SCLK Falling Edge to SDATA Valid Time

Master Clocking in Data

1. See Table 11 for information on other conversion rates.

2. Averaging enabled.

3. Guaranteed by design, not production tested.

4. See SMBus Timing Specifications section for more information.

5. Disabled by default. See the Serial Bus Interface section for details to enable it.

−

25

32

ms

−

−

1

ms

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