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ADT7482 Ver la hoja de datos (PDF) - Analog Devices

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ADT7482 Datasheet PDF : 24 Pages
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ADT7482
TIMING SPECIFICATIONS
Table 2. SMBus Timing Specifications1
Parameter
Limit at TMIN, TMAX
fSCLK
400
tLOW
1.3
tHIGH
0.6
tR
300
tF
300
tSU; STA
600
tHD; STA2
600
tSU; DAT3
100
tSU; STO4
600
tBUF
1.3
1 Guaranteed by design, but not production tested.
2 Time from 10% of SDATA to 90% of SCLK.
3 Time for 10% or 90% of SDATA to 10% of SCLK.
4 Time for 90% of SCLK to 10% of SDATA.
Unit
kHz max
μs min
μs min
ns max
ns max
ns min
ns min
ns min
ns min
μs min
Description
Clock low period, between 10% points.
Clock high period, between 90% points.
Clock/data rise time.
Clock/data fall time.
Start condition setup time.
Start condition hold time.
Data setup time.
Stop condition setup time.
Bus free time between stop and start conditions.
SCLK
SDATA
tBUF
STOP START
tLOW
tR
tHD;STA
tHD;DAT
tF
tHIGH
tSU;DAT
tHD;STA
tSU;STA
START
Figure 2. Serial Bus Timing
tSU;STO
STOP
Rev. 0 | Page 4 of 24

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