ADSP-BF537BBCZ-5AV Ver la hoja de datos (PDF) - Analog Devices
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ADSP-BF537BBCZ-5AV Datasheet PDF : 68 Pages
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ADSP-BF534/ADSP-BF536/ADSP-BF537
(VCO) and the system clock. SCLK divider values are 1 through
15. Table 6 illustrates typical system clock ratios.
Table 6. Example System Clock Ratios
Signal Name
SSEL3–0
0001
0110
1010
Example Frequency Ratios
Divider Ratio
(MHz)
VCO:SCLK VCO
SCLK
1:1
100
100
6:1
300
50
10:1
500
50
Note that the divisor ratio must be chosen to limit the system
clock frequency to its maximum of fSCLK. The SSEL value can be
changed dynamically without any PLL lock latencies by writing
the appropriate values to the PLL divisor register (PLL_DIV).
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
Table 7. This programmable core clock capability is useful for
fast core frequency modifications.
Table 7. Core Clock Ratios
Signal Name
CSEL1–0
00
01
10
11
Example Frequency Ratios
Divider Ratio
(MHz)
VCO:CCLK VCO
CCLK
1:1
300
300
2:1
300
150
4:1
500
125
8:1
200
25
The maximum CCLK frequency not only depends on the part’s
speed grade (see Ordering Guide on Page 67), it also depends on
the applied VDDINT voltage (see Table 10, Table 11, and Table 12
on Page 24 for details). The maximal system clock rate (SCLK)
depends on the chip package and the applied VDDEXT voltage (see
Table 14 on Page 24).
BOOTING MODES
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processor has six
mechanisms (listed in Table 8) for automatically loading inter-
nal and external memory after a reset. A seventh mode is
provided to execute from external memory, bypassing the boot
sequence.
Table 8. Booting Modes
BMODE2 – 0
000
001
010
011
100
Description
Execute from 16-bit external memory (bypass
boot ROM)
Boot from 8-bit or 16-bit memory
(EPROM/flash)
Reserved
Boot from serial SPI memory (EEPROM/flash)
Boot from SPI host (slave mode)
Table 8. Booting Modes (Continued)
BMODE2 – 0
101
110
111
Description
Boot from serial TWI memory (EEPROM/flash)
Boot from TWI host (slave mode)
Boot from UART host (slave mode)
The BMODE pins of the reset configuration register, sampled
during power-on resets and software-initiated resets, imple-
ment the following modes:
• Execute from 16-bit external memory – Execution starts
from address 0x2000 0000 with 16-bit packing. The boot
ROM is bypassed in this mode. All configuration settings
are set for the slowest device possible (3-cycle hold time;
15-cycle R/W access times; 4-cycle setup).
• Boot from 8-bit and 16-bit external flash memory – The
8-bit or 16-bit flash boot routine located in Boot ROM
memory space is set up using asynchronous memory
bank 0. All configuration settings are set for the slowest
device possible (3-cycle hold time; 15-cycle R/W access
times; 4-cycle setup). The Boot ROM evaluates the first
byte of the boot stream at address 0x2000 0000. If it is 0x40,
8-bit boot is performed. A 0x60 byte assumes a 16-bit
memory device and performs 8-bit DMA. A 0x20 byte also
assumes 16-bit memory but performs 16-bit DMA.
• Boot from serial SPI memory (EEPROM or flash) – 8-, 16-,
or 24-bit addressable devices are supported as well as
AT45DB041, AT45DB081, AT45DB161, AT45DB321,
AT45DB642, and AT45DB1282 DataFlash® devices from
Atmel. The SPI uses the PF10/SPI SSEL1 output pin to
select a single SPI EEPROM/flash device, submits a read
command and successive address bytes (0x00) until a valid
8-, 16-, or 24-bit, or Atmel addressable device is detected,
and begins clocking data into the processor.
• Boot from SPI host device – The Blackfin processor oper-
ates in SPI slave mode and is configured to receive the bytes
of the .LDR file from an SPI host (master) agent. To hold
off the host device from transmitting while the boot ROM
is busy, the Blackfin processor asserts a GPIO pin, called
host wait (HWAIT), to signal the host device not to send
any more bytes until the flag is deasserted. The flag is cho-
sen by the user and this information is transferred to the
Blackfin processor via bits 10:5 of the FLAG header.
• Boot from UART – Using an autobaud handshake
sequence, a boot-stream-formatted program is downloaded
by the host. The host agent selects a baud rate within the
UART’s clocking capabilities. When performing the auto-
baud, the UART expects an “@” (boot stream) character
(8 bits data, 1 start bit, 1 stop bit, no parity bit) on the RXD
pin to determine the bit rate. It then replies with an
acknowledgement that is composed of 4 bytes: 0xBF, the
value of UART_DLL, the value of UART_DLH, and 0x00.
The host can then download the boot stream. When the
processor needs to hold off the host, it deasserts CTS.
Therefore, the host must monitor this signal.
Rev. J | Page 16 of 68 | February 2014
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