ADSP-BF537BBCZ-5AV Ver la hoja de datos (PDF) - Analog Devices

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componentes Descripción

Fabricante

ADSP-BF537BBCZ-5AV

Blackfin Embedded Processor

Analog Devices 

ADSP-BF534/ADSP-BF536/ADSP-BF537

Table 9. Pin Descriptions (Continued)

Pin Name

Port H: GPIO/10/100 Ethernet MAC (On

ADSP-BF534, these pins are GPIO only)

PH0 – GPIO/ETxD0

PH1 – GPIO/ETxD1

PH2 – GPIO/ETxD2

PH3 – GPIO/ETxD3

PH4 – GPIO/ETxEN

PH5 – GPIO/MII TxCLK/RMII REF_CLK

PH6 – GPIO/MII PHYINT/RMII MDINT

PH7 – GPIO/COL

PH8 – GPIO/ERxD0

PH9 – GPIO/ERxD1

PH10 – GPIO/ERxD2

PH11 – GPIO/ERxD3

PH12 – GPIO/ERxDV/TACLK5

PH13 – GPIO/ERxCLK/TACLK6

PH14 – GPIO/ERxER/TACLK7

PH15 – GPIO/MII CRS/RMII CRS_DV

Port J: SPORT0/TWI/SPI Select/CAN

PJ0 – MDC

PJ1 – MDIO

PJ2 – SCL

PJ3 – SDA

PJ4 – DR0SEC/CANRX/TACI0

PJ5 – DT0SEC/CANTX/SPI SSEL7

PJ6 – RSCLK0/TACLK2

PJ7 – RFS0/TACLK3

PJ8 – DR0PRI/TACLK4

PJ9 – TSCLK0/TACLK1

PJ10 – TFS0/SPI SSEL3

PJ11 – DT0PRI/SPI SSEL2

Real-Time Clock

RTXI

RTXO

JTAG Port

TCK

TDO

TDI

TMS

TRST

EMU

Type Function

Driver

Type1

I/O GPIO/Ethernet MII or RMII Transmit D0

E

I/O GPIO/Ethernet MII or RMII Transmit D1

E

I/O GPIO/Ethernet MII Transmit D2

E

I/O GPIO/Ethernet MII Transmit D3

E

I/O GPIO/Ethernet MII or RMII Transmit Enable

E

I/O GPIO/Ethernet MII Transmit Clock/RMII Reference Clock

E

I/O GPIO/Ethernet MII PHY Interrupt/RMII Management Data Interrupt (This pin E

should be pulled high when used as a hibernate wake-up.)

I/O GPIO/Ethernet Collision

E

I/O GPIO/Ethernet MII or RMII Receive D0

E

I/O GPIO/Ethernet MII or RMII Receive D1

E

I/O GPIO/Ethernet MII Receive D2

E

I/O GPIO/Ethernet MII Receive D3

E

I/O GPIO/Ethernet MII Receive Data Valid/Alternate Timer5 Input Clock

E

I/O GPIO/Ethernet MII Receive Clock/Alternate Timer6 Input Clock

E

I/O GPIO/Ethernet MII or RMII Receive Error/Alternate Timer7 Input Clock

E

I/O GPIO/Ethernet MII Carrier Sense/Ethernet RMII Carrier Sense and Receive Data E

Valid

O Ethernet Management Channel Clock (On ADSP-BF534 processors, do not E

connect this pin.)

I/O Ethernet Management Channel Serial Data (On ADSP-BF534 processors, tie this E

pin to ground.)

I/O TWI Serial Clock (This pin is an open-drain output and requires a pull-up

F

resistor.)

I/O TWI Serial Data (This pin is an open-drain output and requires a pull-up

F

resistor.)

I

SPORT0 Receive Data Secondary/CAN Receive/Timer0 Alternate Input Capture

O SPORT0 Transmit Data Secondary/CAN Transmit/SPI Slave Select Enable 7

C

I/O SPORT0 Receive Serial Clock/Alternate Timer2 Clock Input

D

I/O SPORT0 Receive Frame Sync/Alternate Timer3 Clock Input

C

I

SPORT0 Receive Data Primary/Alternate Timer4 Clock Input

I/O SPORT0 Transmit Serial Clock/Alternate Timer1 Clock Input

D

I/O SPORT0 Transmit Frame Sync/SPI Slave Select Enable 3

C

O SPORT0 Transmit Data Primary/SPI Slave Select Enable 2

C

I

RTC Crystal Input (This pin should be pulled low when not used.)

O RTC Crystal Output (Does not three-state in hibernate.)

I

JTAG Clock

O JTAG Serial Data Out

C

I

JTAG Serial Data In

I

JTAG Mode Select

I

JTAG Reset (This pin should be pulled low if the JTAG port is not used.)

O Emulation Output

C

Rev. J | Page 21 of 68 | February 2014

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