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ADSP-21992YST
(Rev.:RevPrA)

Mixed Signal DSP Controller With CAN

Analog Devices 

PRELIMINARY TECHNICAL DATA

August 2002

For current information contact Analog Devices at (781) 937-1799

ADSP-21992

the fast, accurate conversion of analog signals needed in

high performance embedded systems. Key features of the

ADC system are:

• 14-bit Pipeline (6-Stage Pipeline) Flash Analog to Digital

Converter.

• 8 Dedicated Analog Inputs.

• Dual Channel Simultaneous Sampling Capability.

• Programmable ADC Clock Rate to Maximum of 20

MSPS.

• First Channel ADC Data Valid approximately 400 ns after

CONVST (at 20 MSPS).

• All 8 Inputs Converted in approximately 800 ns (at 20

MSPS).

• 2.0 V peak to peak Input Voltage Range.

• Multiple Convert Start Sources.

• Internal or External Voltage Reference.

• Out of Range Detection.

• DMA capable transfers from ADC to memory.

The ADC system is based on a pipeline flash converter core,

and contains dual input Sample and Hold amplifiers so that

simultaneous sampling of two input signals is supported.

The ADC system provides an analog input voltage range of

2.0Vpp and provides 14-bit performance with a clock rate

of up to 20 MHz. The ADC system can be programmed to

operate at a clock rate that is programmable from HCLK⁄4

to HCLK⁄30, to a maximum of 20 MHz.

The ADC input structure supports 8 independent analog

inputs; 4 of which are multiplexed into one sample and hold

amplifier (A_SHA) and 4 of which are multiplexed into the

other sample and hold amplifier (B_SHA).

At the 20 MHz HCLK rate, the first data value is valid

approximately 400 ns after the Convert Start command. All

8 channels are converted in approximately 800 ns.

The core of theADSP-21992 provides 14-bit data such that

the stored data values in the ADC data registers are 14-bits

wide.

Voltage Reference

The ADSP-21992 contains an onboard band gap reference

that can be used to provide a precise 1.0V output for use by

the A/D system and externally on the VREF pin for biasing

and level shifting functions. Additionally, the ADSP-21992

may be configured to operate with an external reference

applied to the VREF pin, if required.

PWM Generation Unit

Key features of the three phase PWM Generation Unit are:

• 16-bit, center based PWM Generation Unit

• Programmable PWM Pulsewidth, with resolutions to

12.5 ns (at 80 MHz)

• Single/Double Update Modes

• Programmable Dead Time and Switching Frequency

• Two's Complement Implementation permits smooth

transition into full ON and full OFF states

• Possibility to synchronize the PWM Generation to an

External Synchronization

• Special Provisions for BDCM Operation (Crossover and

Output Enable Functions)

• Wide Variety of Special Switched Reluctance (SR)

Operating Modes

• Output Polarity and Clock Gating Control

• Dedicated Asynchronous PWM Shutdown Signal

• Multiple shut down sources, independently for each unit

The ADSP-21992 integrates a flexible and programmable,

three phase PWM waveform generator that can be pro-

grammed to generate the required switching patterns to

drive a three phase voltage source inverter for ac induction

(ACIM) or permanent magnet synchronous (PMSM)

motor control. In addition, the PWM block contains special

functions that considerably simplify the generation of the

required PWM switching patterns for control of the elec-

tronically commutated motor (ECM) or brushless dc motor

(BDCM). Tying a dedicated pin, PWMSR, to GND,

enables a special mode, for switched reluctance motors

(SRM).

The six PWM output signals consist of three high side drive

pins (AH, BH and CH) and three low side drive signals pins

(AL, BL and CL). The polarity of the generated PWM

signals may be set via hardware by the PWMPOL input pin,

so that either active HI or active LO PWM patterns can be

produced.

The switching frequency of the generated PWM patterns is

programmable using the 16-bit PWMTM register. The

PWM generator is capable of operating in two distinct

modes, single update mode or double update mode. In

single update mode the duty cycle values are programmable

only once per PWM period, so that the resultant PWM

patterns are symmetrical about the midpoint of the PWM

period. In the double update mode, a second updating of

the PWM registers is implemented at the midpoint of the

PWM period. In this mode, it is possible to produce asym-

metrical PWM patterns. that produce lower harmonic

distortion in three phase PWM inverters.

Auxiliary PWM Generation Unit

Key features of the Auxiliary PWM Generation Unit are:

• 16-bit, programmable frequency, programmable duty

cycle PWM outputs

• Independent or offset operating modes

• Double buffered control of duty cycle and period registers

REV. PrA This information applies to a product under development Its characteristics and specifications are subject to change without notice Analog

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Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing

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