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ADSP-21992YST
(Rev.:RevPrA)

Mixed Signal DSP Controller With CAN

Analog Devices 

PRELIMINARY TECHNICAL DATA

August 2002

For current information contact Analog Devices at (781) 937-1799

ADSP-21992

The data bus is configurable to provide an 8 or 16 bit

interface to external memory. Support for word packing lets

the DSP access 16- or 24-bit words from external memory

regardless of the external data bus width.

The memory DMA controller lets the ADSP-21992 move

data and instructions from between memory spaces: inter-

nal-to-external, internal-to-internal, and external-to-

external. On chip peripherals can also use this controller for

DMA transfers.

The embedded ADSP-219x core can respond to up to

seventeen interrupts at any given time: three internal (stack,

emulator kernel, and power down), two external (emulator

and reset), and twelve user defined (peripherals) interrupts.

Programmers assign each of the 32 peripheral interrupt

requests to one of the 12 user defined interrupts. These

assignments determine the priority of each peripheral for

interrupt service.

The following sections provide a functional overview of the

ADSP-21992 peripherals.

Serial Peripheral Interface (SPI) Port

The Serial Peripheral Interface (SPI) Port provides func-

tionality for a generic configurable serial port interface

based on the SPI standard, which enables the DSP to com-

municate with multiple SPI compatible devices. Key

features of the SPI port are:

• Interface to host microcontroller or serial EEPROM

• Master or slave operation (3 Wire Interface MISO,

MOSI, SCK)

• Data rates to 20 Mbaud (16-bit baud rate selector)

• 8 or 16-bit transfer

• Programmable clock phase & polarity

• Broadcast Mode - 1 master, multiple slaves

• DMA capability & Dedicated interrupts

• PF0 can be used as Slave Select Input Line

• PF1-PF7 can be used as external Slave Select output

SPI is a 3 wire interface consisting of 2 data pins (MOSI

and MISO), one clock pin (SCK), and a single Slave Select

input (SPISS0) that is multiplexed with the PF0 Flag IO

line and seven Slave Select outputs (SPISEL1 to SPISEL7)

that are multiplexed with the PF1 to PF7 Flag IO lines. The

SPISS0 input is used to select the ADSP-21992 as a slave

to an external master. The SPISEL1 to SPISEL7 outputs

can be used by the ADSP-21992 (acting as a master) to

select/enable up to seven external slaves in an multi device

SPI configuration. In a multimaster or a multi device con-

figuration, all MOSI pins are tied together, all MISO pins

are tied together, and all SCK pins are tied together.

During transfers, the SPI port simultaneously transmits and

receives by serially shifting data in and out on the serial data

line. The serial clock line synchronizes the shifting and

sampling of data on the serial data line.

In master mode, the DSP’s core performs the following

sequence to set up and initiate SPI transfers:

1. Enables and configures the SPI port operation (data

size, and transfer format).

2. Selects the target SPI slave with the SPISELx output

pin (reconfigured Programmable Flag pin).

3. Defines one or more DMA descriptors in Page 0 of I/O

memory space (optional in DMA mode only).

4. Enables the SPI DMA engine and specifies transfer

direction (optional in DMA mode only).

5. In non DMA mode only, reads or writes the SPI port

receive or transmit data buffer.

The SCK line generates the programmed clock pulses for

simultaneously shifting data out on MOSI and shifting

data in on MISO. In DMA mode only, transfers continue

until the SPI DMA word count transitions from 1 to 0.

In slave mode, the DSP core performs the following

sequence to set up the SPI port to receive data from a master

transmitter:

1. Enables and configures the SPI slave port to match the

operation parameters set up on the master (data size

and transfer format) SPI transmitter.

2. Defines and generates a receive DMA descriptor in

Page 0 of memory space to interrupt at the end of the

data transfer (optional in DMA mode only).

3. Enables the SPI DMA engine for a receive access

(optional in DMA mode only).

4. Starts receiving the data on the appropriate SCK edges

after receiving an SPI chip select on the SPISS0 input

pin (reconfigured Programmable Flag pin)

from a master

In DMA mode only, reception continues until the SPI

DMA word count transitions from 1 to 0. The DSP core

could continue, by queuing up the next DMA descriptor.

A slave mode transmit operation is similar, except the DSP

core specifies the data buffer in memory space from which

to transmit data, generates and relinquishes control of the

transmit DMA descriptor, and begins filling the SPI port

data buffer. If the SPI controller is not ready on time to

transmit, it can transmit a “zero” word.

DSP Serial Port (SPORT)

The ADSP-21992 incorporates a complete synchronous

serial port (SPORT) for serial and multiprocessor commu-

nications. The SPORT supports the following features:

• Bidirectional: the SPORT has independent transmit and

receive sections.

• Double buffered: the SPORT section (both receive and

transmit) has a data register for transferring data words

to and from other parts of the processor and a register for

shifting data in or out. The double buffering provides

additional time to service the SPORT.

REV. PrA This information applies to a product under development Its characteristics and specifications are subject to change without notice Analog

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Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing

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