ADSP-21992(RevPrA) Ver la hoja de datos (PDF) - Analog Devices

Número de pieza

componentes Descripción

Fabricante

ADSP-21992
(Rev.:RevPrA)

Mixed Signal DSP Controller With CAN

Analog Devices 

PRELIMINARY TECHNICAL DATA

August 2002

For current information contact Analog Devices at (781) 937-1799

ADSP-21992

DSP uses slightly different mechanisms to generate a 24-bit

address for each bus. The DSP has three functions that

support access to the full memory map.

• The DAGs generate 24-bit addresses for data fetches from

the entire DSP memory address range. Because DAG

index (address) registers are 16 bits wide and hold the

lower 16 bits of the address, each of the DAGs has its own

8-bit page register (DMPGx) to hold the most significant

eight address bits. Before a DAG generates an address,

the program must set the DAG’s DMPGx register to the

appropriate memory page. The DMPG1 register is also

used as a page register when accessing external memory.

The program must set DMPG1 accordingly, when

accessing data variables in external memory. A 'C'

program macro is provided for setting this register.

• The Program Sequencer generates the addresses for

instruction fetches. For relative addressing instructions,

the program sequencer bases addresses for relative jumps,

calls, and loops on the 24-bit Program Counter (PC). In

direct addressing instructions (two word instructions),

the instruction provides an immediate 24-bit address

value. The PC allows linear addressing of the full 24-bit

address range.

• For indirect jumps and calls that use a 16-bit DAG

address register for part of the branch address, the

Program Sequencer relies on an 8-bit Indirect Jump page

(IJPG) register to supply the most significant eight

address bits. Before a cross page jump or call, the program

must set the program sequencer’s IJPG register to the

appropriate memory page.

The ADSP-21992 has 4K word of on chip ROM that holds

boot routines. The DSP starts executing instructions from

the on chip boot ROM, which starts the boot process. For

more information, see Booting Modes on page 14. The on

chip boot ROM is located on Page 255 in the DSP’s

memory space map, starting at address 0xFF0000.

External (Off Chip) Memory

Each of the ADSP-21992’s off chip memory spaces has a

separate control register, so applications can configure

unique access parameters for each space. The access param-

eters include read and write wait counts, wait state

completion mode, I/O clock divide ratio, write hold time

extension, strobe polarity, and data bus width. The core

clock and peripheral clock ratios influence the external

memory access strobe widths. For more information, see

Clock Signals on page 13. The off chip memory spaces are:

• External memory space (MS3–0 pins)

• I/O memory space (IOMS pin)

• Boot memory space (BMS pin)

All of these off chip memory spaces are accessible through

the External Port, which can be configured for 8-bit or

16-bit data widths.

External Memory Space

External memory space consists of four memory banks.

These banks can contain a configurable number of 64 k

Word pages. At reset, the page boundaries for external

memory have Bank0 containing pages 1 to 63, Bank1 con-

taining pages 64 to 127, Bank2 containing pages 128 to 191,

and Bank3 containing pages 192 to 254. The MS3-MS0

memory bank pins select Banks 3-0, respectively. Both the

ADSP-219x core and DMA capable peripherals can access

the DSP’s external memory space.

All accesses to external memory are managed by the

External Memory Interface Unit (EMI).

I/O Memory Space

The ADSP-21992 supports an additional external memory

called I/O memory space. The IO space consists of 256

pages, each containing 1024 addresses. This space is

designed to support simple connections to peripherals (such

as data converters and external registers) or to bus interface

ASIC data registers. The first 32K addresses (IO pages 0 to

31) are reserved for on chip peripherals. The upper 224k

addresses (IO pages 32 to 255) are available for external

peripheral devices. External I/O pages have their own select

pin (IOMS). The DSP instruction set provides instructions

for accessing I/O space.

0X00::0X000

0X1F::0X3FF

0X20::0X000

ON-CHIP

PERIPHERALS

16-BITS

PAGES 0 TO 31

1024 WORDS/PAGE

2 PERIPHERALS/PAGE

0XFF::0X3FF

OFF-CHIP

PERIPHERALS

16-BITS

PAGES 32 TO 255

1024 WORDS/PAGE

Figure 3. ADSP-21992 I/O Memory Map

Boot Memory Space

Boot memory space consists of one off chip bank with 254

pages. The BMS memory bank pin selects boot memory

space. Both the ADSP-219x core and DMA capable periph-

REV. PrA This information applies to a product under development Its characteristics and specifications are subject to change without notice Analog

5

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing

Share Link: