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ADSP-21992YST
(Rev.:RevPrA)

Mixed Signal DSP Controller With CAN

Analog Devices 

PRELIMINARY TECHNICAL DATA

August 2002

For current information contact Analog Devices at (781) 937-1799

ADSP-21992

ADSP-219X

DSP CORE

INTERRUPT CONTROLLER/

TIMERS/FLAGS

CACHE

64 X 24-BIT

DAG1

DAG2

4 X 4 X 16 4 X 4 X 16

PROGRAM

SEQUENCER

PM ADDRESS BUS

DM ADDRESS BUS

INTERNAL SRAM

TWO INDEPENDENT BLOCKS

ADDRESS

ADDRESS

DATA

DATA

DMA

ADDRESS

DMA

DATA

BUS

CONNECT

(PX)

DATA

REGISTER

FILE

INPUT

REGISTERS

RESULT

REGISTERS

MULT

16 X 16-BIT

PM DATA BUS

DM DATA BUS

AHB CORE

INTERFACE

BARREL

SHIFTER

ALU

I/O REGISTERS

(MEMORY MAPPED)

CONTROL

STATUS

BUFFERS

DMA

CONTROLLER

JTAG

TEST &

EMULATION

EXTERNAL PORT

ADDR BUS

MUX

EXTERNAL MEMORY

INTERFACE

DATA BUS

MUX

EMBEDDED

CONTROL

PERIPHERALS AND

COMMUNICATIONS

PORTS

I/O PROCESSOR

Figure 1. ADSP-21992 DSP Block Diagram

• Architectural enhancements for compiled C code

efficiency

• Architecture enhancements beyond ADSP-218x family

are supported with instruction set extensions for added

registers, ports, and peripherals.

The clock generator module of the ADSP-21992 includes

Clock Control logic that allows the user to select and change

the main clock frequency. The module generates two output

clocks; the DSP core clock, CCLK, and the peripheral

clock, HCLK. CCLK can sustain clock values of up to 160

MHz, while HCLK can be equal to CCLK or CCLK/2 for

values up to a maximum 80MHz peripheral clock.

The ADSP-21992 instruction set provides flexible data

moves and multifunction (one or two data moves with a

computation) instructions. Every single word instruction

can be executed in a single processor cycle. The

ADSP-21992 assembly language uses an algebraic syntax

for ease of coding and readability. A comprehensive set of

development tools supports program development.

The block diagram Figure 1 shows the architecture of the

embedded ADSP-219x core. It contains three independent

computational units: the ALU, the multiplier/accumulator

(MAC), and the shifter. The computational units process

16-bit data from the register file and have provisions to

support multiprecision computations. The ALU performs

a standard set of arithmetic and logic operations; division

primitives are also supported. The MAC performs single

cycle multiply, multiply/add, and multiply/subtract opera-

tions. The MAC has two 40-bit accumulators, which help

with overflow. The shifter performs logical and arithmetic

shifts, normalization, denormalization, and derive exponent

operations. The shifter can be used to efficiently implement

numeric format control, including multiword and block

floating point representations.

Register usage rules influence placement of input and

results within the computational units. For most operations,

the computational units’ data registers act as a data register

file, permitting any input or result register to provide input

to any unit for a computation. For feedback operations, the

computational units let the output (result) of any unit be

REV. PrA This information applies to a product under development Its characteristics and specifications are subject to change without notice Analog

3

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing

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