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ADSP-21992YST
(Rev.:RevPrA)

Mixed Signal DSP Controller With CAN

Analog Devices 

PRELIMINARY TECHNICAL DATA

ADSP-21992

For current information contact Analog Devices at (781) 937-1799

August 2002

Integrated Watchdog Timer

Dedicated Peripheral Interrupt Controller with Software

Priority Control

Multiple Boot Modes

Precision 1.0V Voltage Reference

Integrated Power-On-Reset (POR) Generator

Flexible Power Management with Selectable Powerdown

and Idle Modes

2.5V Internal Operation with 3.3V I/O

Operating Temperature Range of –40ºC to +115ºC

176 pin LQFP package

TARGET APPLICATIONS

Industrial Motor Drives

Un-Interruptible Power Supplies

Optical Networking Control

Data Acquisition Systems

Test and Measurement Systems

Portable Instrumentation

GENERAL NOTE

This data sheet provides preliminary information for the

ADSP-21992 Mixed Signal Digital Signal Processor.

GENERAL DESCRIPTION

The ADSP-21992 is a mixed signal DSP controller based

on the ADSP-219x DSP Core, suitable for a variety of high

performance Industrial Motor Control and Signal Process-

ing applications that require the combination of a high

performance DSP and the mixed signal integration of

embedded control peripherals such as analog to digital con-

version with communications interfaces such as CAN.

The ADSP-21992 integrates the 160 MIPS, fixed point

ADSP-219x family base architecture with a serial port, an

SPI compatible port, a DMA controller, three programma-

ble timers, general purpose Programmable Flag pins,

extensive interrupt capabilities, on chip program and data

memory spaces, and a complete set of embedded control

peripherals that permits fast motor control and signal pro-

cessing in a highly integrated environment.

The ADSP-21992 architecture is code compatible with

previous ADSP-217x based ADMCxxx products. Although

the architectures are compatible, the ADSP-21992, with

ADSP-219x architecture, has a number of enhancements

over earlier architectures. The enhancements to computa-

tional units, data address generators, and program

sequencer make the ADSP-21992 more flexible and easier

to program than the previous ADSP-21xx embedded DSPs.

Indirect addressing options provide addressing flexibility—

premodify with no update, pre- and post-modify by an

immediate 8-bit, two’s complement value and base address

registers for easier implementation of circular buffering.

The ADSP-21992 integrates 48K words of on chip memory

configured as 32K words (24-bit) of program RAM, and

16K words (16-bit) of data RAM.

Fabricated in a high speed, low power, CMOS process, the

ADSP-21992 operates with a 6.25 ns instruction cycle time

(160 MIPS). All instructions, except two multiword

instructions, execute in a single DSP cycle.

The ADSP-21992’s flexible architecture and comprehen-

sive instruction set support multiple operations in parallel.

For example, in one processor cycle, the ADSP-21992 can:

• Generate an address for the next instruction fetch

• Fetch the next instruction

• Perform one or two data moves

• Update one or two data address pointers

• Perform a computational operation

These operations take place while the processor

continues to:

• Receive and transmit data through the serial port

• Receive or transmit data over the SPI port

• Access external memory through the external memory

interface

• Decrement the timers

• Operate the embedded control peripherals (ADC, PWM,

EIU, etc.)

DSP Core Architecture

• 6.25 ns instruction cycle time (internal), for up to 160

MIPS sustained performance

• ADSP-218x family code compatible with the same easy

to use algebraic syntax

• Single cycle instruction execution

• Up to 1 Mwords of addressable memory space with

twenty four bits of addressing width

• Dual purpose program memory for both instruction and

data storage

• Fully transparent Instruction Cache allows dual operand

fetches in every instruction cycle

• Unified memory space permits flexible address genera-

tion, using two independent DAG units

• Independent ALU, Multiplier/Accumulator, and barrel

Shifter computational units with dual 40-bit

accumulators

• Single cycle context switch between two sets of computa-

tional and DAG registers

• Parallel execution of computation and memory

instructions

• Pipelined architecture supports efficient code execution

at speeds up to 160 MIPS

• Register file computations with all non-conditional,

non-parallel computational instructions

• Powerful Program Sequencer provides zero overhead

looping and conditional instruction execution

2 This information applies to a product under development Its characteristics and specifications are subject to change without notice Analog

Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing

REV. PrA

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