ADSP-2192M Ver la hoja de datos (PDF) - Analog Devices
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ADSP-2192M Datasheet PDF : 40 Pages
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ADSP-2192M
register reaches zero, a PCI interrupt can be generated. Also, the
Interrupt Count register will be reloaded from the Interrupt Base
Count and continue counting down for the next interrupt.
Table 5. PCI Interrupt Register
Bit Name
Comments
0 Reserved
Reserve
1 Rx0 DMA Channel Receive Channel 0 Bus
Interrupt
Master Transactions
2 Rx1 DMA Channel Receive Channel 1 Bus
Interrupt
Master Transactions
3 Tx0 DMA Channel Transmit Channel 0 Bus
Interrupt
Master Transactions
4 Tx1 DMA Channel Transmit Channel 1 Bus
Interrupt
Master Transactions
5 Incoming Mailbox PCI to DSP Mailbox 0
0 PCI Interrupt Transfer
6 Incoming Mailbox PCI to DSP Mailbox 1
1 PCI Interrupt Transfer
7 Outgoing Mailbox DSP to PCI Mailbox 0
0 PCI Interrupt Transfer
8 Outgoing Mailbox DSP to PCI Mailbox 1
1 PCI Interrupt Transfer
9 Reserved
10 Reserved
11 I/O Wake-up
I/O Pin Initiated
12 AC’97 Wake-up AC’97 Interface Initiated
13 PCI Master Abort PCI Interface Master Abort
Interrupt
Detected
14 PCI Target Abort PCI Interface Target Abort
Interrupt
Detected
15 Reserved
PCI Interrupts
There are a variety of potential sources of interrupts to the PCI
host besides the bus master DMA interrupts. A single interrupt
pin, INTA is used to signal these interrupts back to the host. The
PCI Interrupt Register consolidates all of the possible interrupt
sources; the bits of this register are shown in Table 5. The register
bits are set by the various sources, and can be cleared by writing
a 1 to the bit(s) to be cleared.
PCI Control Register.
This register must be initialized by the DSP ROM code prior to
PCI enumeration. (It has no effect in ISA or USB mode.) Once
the Configuration Ready bit has been set to 1, the PCI Control
Register becomes read-only, and further access by the DSP to
configuration space is disallowed. The bits of this register are
shown in Table 6.
PCI Configuration Space
The ADSP-2192M PCI Interface provides three separate con-
figuration spaces, one for each possible function. This document
describes the registers in each function, their reset condition, and
how the three functions interact to access and control the ADSP-
2192M hardware.
Table 6. PCI Control Register
Bit Name
1–0 PCI Functions
Configured
2
Configuration
Ready
15–3 Reserved
Comments
00 = One PCI function
enabled, 01 = Two functions,
10 = Three functions
When 0, disables PCI accesses
to the ADSP-2192M (termi-
nated with Retry). Must be set
to 1 by DSP ROM code after
initializing configuration
space. Once 1, cannot be
written to 0.
Similarities Between the Three PCI Functions
Each function contains a complete set of registers in the pre-
defined header region as defined in the PCI Local Bus
Specification Revision 2.2. In addition, each function contains
the optional registers to support PCI Bus Power Management.
Generally, registers that are unimplemented or read-only in one
function are similarly defined in the other functions. Each
function contains four base address registers that are used to
access ADSP-2192M control registers and DSP memory.
Base address register (BAR) 1 is used to access the ADSP-
2192M control registers. Accesses to the control registers via
BAR1 uses PCI memory accesses. BAR1 requests a memory
allocation of 1024 bytes. Access to DSP memory occurs via
BAR2 and BAR3. BAR2 is used to access 24-bit DSP memory
(for DSP program downloading) while BAR3 is used to access
16-bit DSP memory. BAR4 provides I/O space access to both the
control registers and the DSP memory.
Table 7 shows the configuration space headers for the three
spaces. While these are the default uses for each of the configu-
rations, they can be redefined to support any possible function
by writing to the class code register of that function during boot.
Additionally, during boot time, the DSP can disable one or more
of the functions. If only two functions are enabled, they will be
functions 0 and 1. If only one function is enabled, it will be
function 0.
Interactions Between the Three PCI Configurations
Because the configurations must access and control a single set
of resources, potential conflicts can occur between the control
specified by the configuration.
Target accesses to registers and DSP memory can go through any
function. As long as the Memory Space access enable bit is set in
that function, then PCI memory accesses whose addresses match
the locations programmed into a function, BARs 1–3 will be able
to read or write any visible register or memory location within the
ADSP-2192M. Similarly, if I/O space access enable is set, then
PCI I/O accesses can be performed via BAR4.
Within the Power Management section of the configuration
blocks, there are a few interactions. The part will stay in the
highest power state between the three configurations.
REV. 0
–9–
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