ADSP-2184L Ver la hoja de datos (PDF) - Analog Devices
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ADSP-2184L Datasheet PDF : 48 Pages
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ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L
faster rate than can be serviced, due to the additional time the
processor takes to come out of the idle state (a maximum of n
processor cycles).
SYSTEM INTERFACE
Figure 2 shows typical basic system configurations with the
ADSP-218xL series, two serial devices, a byte-wide EPROM,
and optional external program and data overlay memories
(mode-selectable). Programmable wait state generation allows
the processor to connect easily to slow peripheral devices.
ADSP-218xL series members also provide four external inter-
rupts and two serial ports or six external interrupts and one
serial port. Host Memory Mode allows access to the full external
data bus, but limits addressing to a single address bit (A0).
Through the use of external hardware, additional system
peripherals can be added in this mode to generate and latch
address signals.
Clock Signals
ADSP-218xL series members can be clocked by either a crystal
or a TTL-compatible clock signal.
The CLKIN input cannot be halted, changed during operation,
nor operated below the specified frequency during normal oper-
ation. The only exception is while the processor is in the
power-down state. For additional information, refer to the
ADSP-218x DSP Hardware Reference, for detailed information
on this power-down feature.
If an external clock is used, it should be a TTL-compatible signal
running at half the instruction rate. The signal is connected to
the processor’s CLKIN input. When an external clock is used,
the XTAL pin must be left unconnected.
ADSP-218xL series members use an input clock with a fre-
quency equal to half the instruction rate; a 40 MHz input clock
yields a 12.5 ns processor cycle (which is equivalent to
80 MHz). Normally, instructions are executed in a single pro-
cessor cycle. All device timing is relative to the internal
instruction clock rate, which is indicated by the CLKOUT signal
when enabled.
Because ADSP-218xL series members include an on-chip oscil-
lator circuit, an external crystal may be used. The crystal should
be connected across the CLKIN and XTAL pins, with two
capacitors connected as shown in Figure 3. Capacitor values are
dependent on crystal type and should be specified by the crystal
manufacturer. A parallel-resonant, fundamental frequency,
microprocessor-grade crystal should be used. To provide an
adequate feedback path around the internal amplifier circuit,
place a resistor in parallel with the circuit, as shown in Figure 3.
A clock output (CLKOUT) signal is generated by the processor
at the processor’s cycle rate. This can be enabled and disabled by
the CLKODIS bit in the SPORT0 Autobuffer Control Register.
1/2 ؋ CLOCK
OR
C RY STA L
SERIAL
DEVICE
SERIAL
DEVICE
FULL MEMORY MODE
A D SP -21 8xL
CLKIN
XTAL
ADDR13–0 14
A13–0
FL0–2
D23–16 A0–A21
IRQ2/PF7
24
IRQE/PF4 DATA23–0
IR QL 0 /P F5
IR QL 1 /P F6
BMS
D15–8
DATA
CS
BYTE
MEMORY
WR
A10–0
MODE D/PF3
MODE C/PF2
MODE A/PF0
MODE B/PF1
SPORT1
SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI
SPORT0
SCLK0
RD
IOMS
PMS
CDBMMRSSInsert
systDADem212333–––i008nterfDADACaAADDScTTDDeAARRdiaP2g(0MPr4EOaM8TITS/RmVOWWEELIEPGOMOOSRHhMCOP8L8EeAAERKKARrTNCYeYAIETOLSNSS)
DM SEGMENTS
RFS0
BG
TFS0
BGH
DT0
DR0
PWD
PWDACK
1/2 ؋ CLOCK
OR
CRYSTAL
SERIAL
D E V IC E
SERIAL
DEVICE
SYSTEM
INTE RFA C E
OR
µCONTROLLER
HOST MEMORY MODE
ADSP-218xL
CLK IN
XTAL
FL0–2
1
A0
IRQ2/PF7
16
IRQE/PF4 DATA23–8
IRQ L0/PF 5
IRQL1/PF6
BMS
MODE D/PF3
WR
MODE C/PF2
MODE A/PF0
RD
MODE B/PF1
SPORT1
IOMS
SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI
PMS
SPORT0
SC LK0
RFS0
TFS0
DT0
DMS
CMS
BR
BG
DR0
BGH
IDMA PORT
PWD
IRD/D6
PW DACK
IWR/D7
IS/D4
IAL/D5
IACK/D3
IAD15-0
16
NOTE: MODE D APPLIES TO THE ADSP-2187L PROCESSOR ONLY
Figure 2. Basic System Interface
Rev. C | Page 7 of 48 | January 2008
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