ADSP-2184BST-160 Ver la hoja de datos (PDF) - Analog Devices

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ADSP-2184BST-160

DSP Microcomputer

Analog Devices 

ADSP-2184

Common-Mode Pins

Pin

Name(s)

RESET

BR

BG

BGH

DMS

PMS

IOMS

BMS

CMS

RD

WR

IRQ2/

PF7

IRQL0/

PF5

IRQL1/

PF6

IRQE/

PF4

PF3

Mode C/

PF2

Mode B/

PF1

Mode A/

PF0

CLKIN, XTAL

CLKOUT

SPORT0

SPORT1/

IRQ1:0

FI, FO

PWD

PWDACK

FL0, FL1, FL2

VDD and GND

EZ-Port

# Input/

of Out-

Pins put Function

1I

1I

1O

1O

1O

1O

1O

1O

1O

1O

1O

1I

I/O

1I

I/O

1I

I/O

1I

I/O

1 I/O

1I

I/O

1I

I/O

1I

I/O

2I

1O

5 I/O

5 I/O

1I

1O

3O

16 I

9 I/O

Processor Reset Input

Bus Request Input

Bus Grant Output

Bus Grant Hung Output

Data Memory Select Output

Program Memory Select Output

I/O Memory Select Output

Byte Memory Select Output

Combined Memory Select Output

Memory Read Enable Output

Memory Write Enable Output

Edge- or Level-Sensitive

Interrupt Request1

Programmable I/O Pin

Level-Sensitive Interrupt Requests1

Programmable I/O Pin

Level-Sensitive Interrupt Requests1

Programmable I/O Pin

Edge-Sensitive Interrupt Requests1

Programmable I/O Pin

Programmable I/O Pin

Mode Select Input—Checked

only During RESET

Programmable I/O Pin During

Normal Operation

Mode Select Input—Checked

only During RESET

Programmable I/O Pin During

Normal Operation

Mode Select Input—Checked

only During RESET

Programmable I/O Pin During

Normal Operation

Clock or Quartz Crystal Input

Processor Clock Output

Serial Port I/O Pins

Serial Port I/O Pins

Edge- or Level-Sensitive Interrupts,

Flag In, Flag Out2

Power-Down Control Input

Power-Down Control Output

Output Flags

Power and Ground

For Emulation Use

NOTES

1Interrupt/Flag pins retain both functions concurrently. If IMASK is set to

enable the corresponding interrupts, the DSP will vector to the appropriate

interrupt vector address when the pin is asserted, either by external devices or

set as a programmable flag.

2SPORT configuration determined by the DSP System Control Register. Soft-

ware configurable.

Memory Interface Pins

The ADSP-2184 processor can be used in one of two modes:

Full Memory Mode, which allows BDMA operation with full

external overlay memory and I/O capability, or Host Mode,

which allows IDMA operation with limited external addressing

capabilities. The operating mode is determined by the state of

the Mode C pin during RESET and cannot be changed while

the processor is running.

Full Memory Mode Pins (Mode C = 0)

#

of Input/

Pin Name Pins Output Function

A13:0

D23:0

14 O

24 I/O

Address Output Pins for Pro-

gram, Data, Byte and I/O Spaces

Data I/O Pins for Program,

Data, Byte and I/O Spaces

(8 MSBs Are Also Used as

Byte Memory Addresses)

Host Mode Pins (Mode C = 1)

#

of Input/

Pin Name Pins Output Function

IAD15:0 16 I/O

A0

1

O

D23:8

IWR

IRD

IAL

IS

IACK

16 I/O

1

I

1

I

1

I

1

I

1

O

IDMA Port Address/Data Bus

Address Pin for External I/O,

Program, Data, or Byte Access

Data I/O Pins for Program,

Data Byte and I/O Spaces

IDMA Write Enable

IDMA Read Enable

IDMA Address Latch Pin

IDMA Select

IDMA Port Acknowledge

In Host Mode, external peripheral addresses can be decoded using the A0,

BMS, CMS, PMS, DMS, and IOMS signals.

Setting Memory Mode

Memory Mode selection for the ADSP-2184 is made during

chip reset through the use of the Mode C pin. This pin is multi-

plexed with the DSP’s PF2 pin, so care must be taken in how

the mode selection is made. The two methods for selecting the

value of Mode C are passive and active.

Passive configuration involves the use a pull-up or pull-down

resistor connected to the Mode C pin. To minimize power

consumption, or if the PF2 pin is to be used as an output in the

DSP application, a weak pull-up or pull-down, on the order of

100 kΩ, can be used. This value should be sufficient to pull the

pin to the desired level and still allow the pin to operate as a

programmable flag output without undue strain on the processor’s

output driver. For minimum power consumption during

power-down, reconfigure PF2 to be an input, as the pull-up or

pull-down will hold the pin in a known state, and will not switch.

Active configuration involves the use of a three-stateable exter-

nal driver connected to the Mode C pin. A driver’s output en-

able should be connected to the DSP’s RESET signal such that

it only drives the PF2 pin when RESET is active (low). After

RESET is deasserted, the driver should three-state, thus allow-

ing full use of the PF2 pin as either an input or output.

–4–

REV. 0

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