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Fabricante

ADSP-21363SBBC-ENG

SHARC® Processor

Analog Devices 

ADSP-21363

Preliminary Technical Data

CLOCK

2

2

3

ADC

(OP TIONAL)

CLK

FS

S DAT

DAC

(OP TIONAL)

CLK

FS

S DAT

CLKI N

XTAL

CLK_CFG 1-0

BOOTCFG1-0

FLAG 3-1

ADSP-21363

CLKOUT

ALE

AD15-0

RD

WR

FLAG 0

DAI_P1

DAI _P 2

DAI _P 3

DAI_ P1 8

DAI_P19

DAI_ P20

SRU

SCLK0

SFS 0

SD0 A

SD0 B

SPO RT0

SP ORT1

SPO RT2

SPO RT3

SPORT4

SPO RT5

DAI

RES ET

CLK

FS

P CGA

PCGB

JTAG

6

LATCH

ADDR

DATA

OE

WE

CS

PARALLE L

PO RT

RAM

BOOT ROM

I/O DEVICE

Figure 2. ADSP-21363 System Sample Configuration

element are arranged in parallel, maximizing computational

throughput. Single multifunction instructions execute parallel

ALU and multiplier operations. In SIMD mode, the parallel

ALU and multiplier operations occur in both processing ele-

ments. These computation units support IEEE 32-bit single-

precision floating-point, 40-bit extended precision floating-

point, and 32-bit fixed-point data formats.

Data Register File

A general-purpose data register file is contained in each

processing element. The register files transfer data between the

computation units and the data buses, and store intermediate

results. These 10-port, 32-register (16 primary, 16 secondary)

register files, combined with the ADSP-2136x enhanced Har-

vard architecture, allow unconstrained data flow between

computation units and internal memory. The registers in PEX

are referred to as R0-R15 and in PEY as S0-S15.

Single-Cycle Fetch of Instruction and Four Operands

The ADSP-21363 features an enhanced Harvard architecture in

which the data memory (DM) bus transfers data and the pro-

gram memory (PM) bus transfers both instructions and data

(see Figure 1 on Page 1). With the ADSP-21363’s separate pro-

gram and data memory buses and on-chip instruction cache,

the processor can simultaneously fetch four operands (two over

each data bus) and one instruction (from the cache), all in a sin-

gle cycle.

Instruction Cache

The ADSP-21363 includes an on-chip instruction cache that

enables three-bus operation for fetching an instruction and four

data values. The cache is selective—only the instructions whose

fetches conflict with PM bus data accesses are cached. This

cache allows full-speed execution of core, looped operations

such as digital filter multiply-accumulates, and FFT butterfly

processing.

Data Address Generators With Zero-Overhead Hardware

Circular Buffer Support

The ADSP-21363’s two data address generators (DAGs) are

used for indirect addressing and implementing circular data

buffers in hardware. Circular buffers allow efficient program-

ming of delay lines and other data structures required in digital

signal processing, and are commonly used in digital filters and

Fourier transforms. The two DAGs of the ADSP-21363 contain

sufficient registers to allow the creation of up to 32 circular buff-

ers (16 primary register sets, 16 secondary). The DAGs

automatically handle address pointer wraparound, reduce over-

head, increase performance, and simplify implementation.

Circular buffers can start and end at any memory location.

Rev. PrA | Page 4 of 44 | September 2004

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