ADSP-21266(RevC) Ver la hoja de datos (PDF) - Analog Devices

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ADSP-21266
(Rev.:RevC)

SHARC® Embedded Processor

Analog Devices 

ADSP-21266

ADDRESS

LONG WORD

ADDRESS

SPACE

NORMAL WORD

ADDRESS

SPACE

SHORT WORD

ADDRESS

SPACE

IOP REGISTERS

BLOCK 0 SRAM (1M BIT)

RESERVED

BLOCK 0 ROM (2M BIT)

BLOCK 1 SRAM (1M BIT)

RESERVED

BLOCK 1 ROM (2M BIT)

BLOCK 0 SRAM (1M BIT)

RESERVED

BLOCK 0 ROM (2M BIT)2

BLOCK 1 SRAM (1M BIT)

RESERVED

BLOCK 1 ROM (2M BIT)3

BLOCK 0 SRAM (1M BIT)

RESERVED

BLOCK 0 ROM (2M BIT)

BLOCK 1 SRAM (1M BIT)

RESERVED

BLOCK 1 ROM (2M BIT)

INTERNAL MEMORY

SPACE

0x0000 0000–0x0003 FFFF

0x0004 0000

0x0004 3FFF

0x0004 4000–0x0005 7FFF

0x0005 8000

0x0005 FFFF

0x0006 0000

0x0006 3FFF

0x0006 4000–0x0007 7FFF

0x0007 8000

0x0007 FFFF

0x0008 0000

0x0008 7FFF

0x0008 8000–0x000A FFFF

0x000B 0000

0x000B FFFF

0x000C 0000

0x000C 7FFF

0x000C 8000–0x000E FFFF

0x000F 0000

0x000F FFFF

0x0010 0000

0x0010 FFFF

0x0011 0000–0x0015 FFFF

0x0016 0000

0x0017 FFFF

0x0018 0000

0x0018 FFFF

0x0019 0000–0x001D FFFF

0x001E 0000

0x001F FFFF

RESERVED

ADDRESS

0x0020 0000

0x00FF FFFF

0x0100 0000

EXTERNAL DMA

ADDRESS SPACE1, 4

RESERVED

EXTERNAL MEMORY

SPACE

0x02FF FFFF

0x0300 0000

0x3FFF FFFF

1EXTERNAL MEMORY IS NOT DIRECTLY ACCESSIBLE BY THE

CORE. DMA MUST BE USED TO READ OR WRITE TO THIS

MEMORY USING THE SPI OR PARALLEL PORT.

2BLOCK 0 ROM HAS A 48-BIT ADDRESS RANGE

(0x000A 0000–0x000A AAAA).

3BLOCK 1 ROM HAS A 48-BIT ADDRESS RANGE

(0x000E 0000–0x000E AAAA).

4USE THE EXTERNAL ADDRESSES LISTED HERE WITH THE

PARALLEL PORT DMA REGISTERS. THE PARALLEL PORT

GENERATES ADDRESS WITHIN THE RANGE

0x0000 0000–0x00FF FFFF.

Figure 3. ADSP-21266 Memory Map

serial ports are made up of two data lines, a clock, and frame

sync. The data lines can be programmed to either transmit or

receive and each data line has its own dedicated DMA channel.

Serial ports are enabled via 12 programmable and simultaneous

receive or transmit pins that support up to 24 transmit or 24

receive channels of audio data when all six SPORTs are enabled,

or six full duplex TDM streams of 128 channels per frame.

The serial ports operate at up to one-quarter of the DSP core

clock rate, providing each with a maximum data rate of

50M bits/sec for a 200 MHz core and 37.5M bits/sec for a

150 MHz core. Serial port data can be automatically transferred

to and from on-chip memory via a dedicated DMA. Each of the

serial ports can work in conjunction with another serial port to

provide TDM support. One SPORT provides two transmit sig-

nals while the other SPORT provides two receive signals. The

frame sync and clock are shared.

Serial ports operate in four modes:

• Standard DSP serial mode

• Multichannel (TDM) mode

• I2S mode

• Left-justified sample pair mode

Rev. C | Page 7 of 44 | October 2007

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