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ADSP-21266
(Rev.:RevC)

SHARC® Embedded Processor

Analog Devices 

ADSP-21266

KEY FEATURES

Serial ports offer left-justified sample-pair and I2S support

via 12 programmable and simultaneous receive or trans-

mit pins, which support up to 24 transmit or 24 receive I2S

channels of audio when all 6 serial ports (SPORTs) are

enabled or 6 full duplex TDM streams of up to 128

channels per frame

At 200 MHz (5 ns) core instruction rate, the ADSP-21266

operates at 1200 MFLOPS peak/800 MFLOPS sustained

performance whether operating on fixed- or floating-point

data; 400 MMACS sustained performance at 200 MHz

Super Harvard Architecture—three independent buses for

dual data fetch, instruction fetch, and nonintrusive, zero-

overhead I/O

2M bits on-chip dual-ported SRAM (1M bit block 0, 1M bit

block 1) for simultaneous access by core processor and

DMA

4M bits on-chip dual-ported mask-programmable ROM

(2M bits in block 0 and 2M bits in block 1)

Dual data address generators (DAGs) with modulo and bit-

reverse addressing

Zero-overhead looping with single-cycle loop setup,

providing efficient program sequencing

Single instruction multiple data (SIMD) architecture

provides:

Two computational processing elements

Concurrent execution—each processing element executes

the same instruction, but operates on different data

Parallelism in buses and computational units allows single

cycle executions (with or without SIMD) of a multiply

operation; an ALU operation; a dual memory read or

write; and an instruction fetch

Transfers between memory and core at up to four 32-bit

floating- or fixed-point words per cycle, sustained

2.4 GBps bandwidth at 200 MHz core instruction rate; 900

Mbps is available via DMA

Accelerated FFT butterfly computation through a multiply

with add and subtract instruction

DMA controller supports:

22 zero-overhead DMA channels for transfers between the

ADSP-21266 internal memory and serial ports (12), the

input data ports (IDP) (eight), the SPI-compatible port

(one), and the parallel port (one)

32-bit background DMA transfers at core clock speed, in

parallel with full-speed processor execution

JTAG background telemetry for enhanced emulation

features

IEEE 1149.1 JTAG standard test access port and on-chip

emulation

Dual voltage: 3.3 V I/O, 1.2 V core

Available in 136-ball BGA and 144-lead LQFP packages; avail-

able in RoHS compliant packages

Digital audio interface includes six serial ports, two precision

clock generators, an input data port, three programmable

timers, and a signal routing unit

Asynchronous parallel/external port provides:

Access to asynchronous external memory

16 multiplexed address/data lines that can support 24-bit

address external address range with 8-bit data or 16-bit

address external address range with 16-bit data

66M byte/sec transfer rate for 200 MHz core rate

50M byte/sec transfer rate for 150 MHz core rate

256 word page boundaries

External memory access in a dedicated DMA channel

8- to 32-bit and 16- to 32-bit word packing options

Programmable wait state options: 2 to 31 CCLKs

Serial ports provide:

Six dual data line serial ports that operate at up to

50M bits/sec for a 200 MHz core and up to 37.5M bits/sec

for a 150 MHz core on each data line—each has a clock,

frame sync, and two data lines that can be configured as

either a receiver or transmitter pair

Left-justified sample-pair and I2S support, programmable

direction for up to 24 simultaneous receive or transmit

channels using two I2S-compatible stereo devices per

serial port

TDM support for telecommunications interfaces including

128 TDM channel support for newer telephony inter-

faces such as H.100/H.110

Up to 12 TDM stream support, each with 128 channels

per frame

Companding selection on a per channel basis in TDM mode

Input data port provides an additional input path to the

SHARC core configurable as either eight channels of I2S or

serial data or as seven channels plus a single 20-bit wide

synchronous parallel data acquisition port

Supports receive audio channel data in I2S, left-justified

sample pair, or right-justified mode

Signal routing unit (SRU) provides configurable and flexible

connections between all DAI components, six serial ports,

two precision clock generators, three timers, an input data

port/parallel data acquisition port, 10 interrupts, six flag

inputs, six flag outputs, and 20 SRU I/O pins (DAI_Px)

Serial peripheral interface (SPI)

Master or slave serial boot through SPI

Full-duplex operation

Master-slave mode multimaster support

Open-drain outputs

Programmable baud rates, clock polarities, and phases

3 muxed flag/IRQ lines

1 muxed flag/timer expired line

ROM-based security features:

JTAG access to memory permitted with a 64-bit key

Protected memory regions that can be assigned to limit

access under program control to sensitive code

PLL has a wide variety of software and hardware multi-

plier/divider ratios

Rev. C | Page 2 of 44 | October 2007

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