ADSP-21261SKBC-150 Ver la hoja de datos (PDF) - Analog Devices

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ADSP-21261SKBC-150

SHARC® Embedded Processor

Analog Devices 

ADSP-21261

ADDITIONAL KEY FEATURES

1M bit on-chip dual-ported SRAM (0.5M bit block 0, 0.5M bit

block 1) for simultaneous access by core processor and

DMA

3M bit on-chip dual-ported mask-programmable ROM

(1.5M bit in block 0 and 1.5M bit in block 1)

Dual data address generators (DAGs) with modulo and bit-

reverse addressing

Zero-overhead looping with single-cycle loop setup,

providing efficient program sequencing

Single-instruction, multiple-data (SIMD) architecture

provides:

Two computational processing elements

Concurrent execution—each processing element executes

the same instruction, but operates on different data

Parallelism in buses and computational units allows single

cycle executions (with or without SIMD) of a multiply

operation; an ALU operation; a dual memory read or

write; and an instruction fetch

Accelerated FFT butterfly computation through a multiply

with add and subtract instruction

DMA controller supports:

18 zero-overhead DMA channels for transfers between the

ADSP-21261 internal memory and serial ports (eight),

the input data port (IDP) (eight), the SPI-compatible port

(one), and the parallel port (one)

32-bit background DMA transfers at core clock speed, in

parallel with full-speed processor execution

JTAG background telemetry for enhanced emulation

features

IEEE 1149.1 JTAG standard test access port and on-chip

emulation

Dual voltage: 3.3 V I/O, 1.2 V core

Available in 136-ball BGA and 144-lead LQFP packages

Also available in lead-free packages

Digital applications interface includes four serial ports, two

precision clock generators, an input data port, three pro-

grammable timers, and a signal routing unit

Asynchronous parallel/external port provides:

Access to asynchronous external memory

16 multiplexed address/data lines that can support 24-bit

address external address range with 8-bit data or 16-bit

address external address range with 16-bit data

50M byte/s transfer rate for 150 MHz core rate

256 word page boundaries

External memory access in a dedicated DMA channel

8-bit to 32-bit and 16-bit to 32-bit word packing options

Programmable wait state options: 2 to 31 CCLK

Serial ports provide:

Four dual data line serial ports that operate at up to

37.5M bit/s for a 150 MHz core on each data line—each

has a clock, frame sync, and two data lines that can be

configured as either a receiver or transmitter pair

Left-justified sample-pair and I2S support, programmable

direction for up to 16 simultaneous receive or transmit

channels using two I2S-compatible stereo devices per

serial port

TDM support for telecommunications interfaces including

128 TDM channel support for newer telephony inter-

faces such as H.100/H.110

Up to 12 TDM stream support, each with 128 channels

per frame

Companding selection on a per channel basis in TDM mode

Input data port provides an additional input path to the

SHARC core configurable as either eight channels of I2S or

serial data or as seven channels plus a single 20-bit wide

synchronous parallel data acquisition port

Supports receive audio channel data in I2S, left-justified

sample pair, or right-justified mode

Signal routing unit (SRU) provides configurable and flexible

connections between all DAI components, four serial

ports, two precision clock generators, three timers, an

input data port/parallel data acquisition port, 10 inter-

rupts, six flag inputs, six flag outputs, and 20 SRU I/O pins

(DAI_Px)

Serial peripheral interface (SPI)

Master or slave serial boot through SPI

Full-duplex operation

Master-slave mode multimaster support

Open-drain outputs

Programmable baud rates, clock polarities, and phases

3 Muxed Flag/IRQ lines

1 Muxed Flag/Timer expired line

ROM-based security features:

JTAG access to memory permitted with a 64-bit key

Protected memory regions that can be assigned to limit

access under program control to sensitive code

PLL has a wide variety of software and hardware multi-

plier/divider ratios

Rev. 0 | Page 2 of 44 | March 2006

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