ADSP-21161N Ver la hoja de datos (PDF) - Analog Devices

Número de pieza

componentes Descripción

Fabricante

ADSP-21161N

SHARC Processor

Analog Devices 

ADSP-21161N

SYNCHRONOUS EP

MULTIPROCESSING

SBSRAM

ASYNCHRONOUS EP

HOST

SRAM

HARDWARE

INTERRUPT

I/O FLAG

TIMER

CLKIN

(CRYSTAL OSCILLATOR

4.2–55 MHz)

XTAL

(QUARTZ CRYSTAL

27.5 MHz MAX)

CLOCK DOUBLER

x1, x2

RATIOS

x2, x3, x4

PLL

CLKDBL

CLKOUT

CLK_CFG1–0

Figure 8. Core Clock and System Clock Relationship to CLKIN

Table 7. CLKOUT and CCLK Clock Generation Operation

Timing Requirements

Description1

CLKIN

Input Clock

CLKOUT

External Port System Clock

PLLICLK

PLL Input Clock

CCLK

Core Clock

tCK

tCCLK

tLCLK

tSCLK

tSDK

tSPICLK

CLKIN Clock Period

(Processor) Core Clock Period

Link Port Clock Period

Serial Port Clock Period

SDRAM Clock Period

SPI Clock Period

1 where:

LR = link port-to-core clock ratio (1, 2, 3, or 1:4, determined by LxCLKD)

SR = serial port-to-core clock ratio (wide range, determined by CLKDIV)

SDCKR = SDRAM-to-Core Clock Ratio (1:1 or 1:2, determined by SDCTL register)

SPIR = SPI-to-Core Clock Ratio (wide range, determined by SPICTL register)

LCLK = Link Port Clock

SCLK = Serial Port Clock

SDK = SDRAM Clock

SPICLK = SPI Clock

POWER DISSIPATION

Total power dissipation has two components: one due to inter-

nal circuitry and one due to the switching of external output

drivers.

Internal power dissipation depends on the instruction execution

sequence and the data operands involved. Using the current

specifications (IDDINPEAK, IDDINHIGH, IDDINLOW, IDDIDLE) from the

Electrical Characteristics on Page 18 and the current-versus-

operation information in Table 8, the programmer can estimate

the ADSP-21161N’s internal power supply (VDDINT) input cur-

rent for a specific application, according to the following

formula:

% Peak  IDD-INPEAK

% High  IDD-INHIGH

% Low  IDD-INLOW

+ % Peak  IDD-IDLE

= IDDINT

Rev. C | Page 20 of 60 | January 2013

CORE

I/O PROCESSOR

LINK PORTS

x1, x1/2, x1/3, x1/4

SDRAM

x1, x1/2

SERIAL PORTS

x1/2 MAX

SPI

x1/8 MAX

Calculation

1/tCK

1/tCKOP

1/tPLLIN

1/tCCLK

1/CLKIN

1/CCLK

(tCCLK) LR

(tCCLK)  SR

(tCCLK)  SDCKR

(tCCLK)  SPIR

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