ADSP-21161NKCA-100(RevA) Ver la hoja de datos (PDF) - Analog Devices

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ADSP-21161NKCA-100
(Rev.:RevA)

DSP Microcomputer

Analog Devices 

ADSP-21161N

CLOCK RESET

ADSP-21161N #4

ADSP-21161N #3

CLKIN

RESET

ADDR23-0

DATA47-16

3

ID2-0

CONTROL

ADSP-21161N #2

CLKIN

RESET

ADDR23-0

DATA47-16

2

ID2-0

CONTROL

ADSP-21161N #1

BMS

CLKIN

RESET

ADDR23-0

DATA47-16

RD

1

ID2-0

WR

ACK

MS3-0

SBTS

CS

HBR

HBG

REDY

BR6-2

BR1

RAS

CAS

DQM

SDWE

SDCLK1-0

SDCKE

SDA10

ADDR

DATA

CS

BOOT

EPROM

(OPTIONAL)

ADDR

DATA

OE

WE

ACK

GLOBAL

MEMORY

AND

PERIPHERALS

(OPTIONAL)

CS

ADDR

DATA

HOST

PROCESSOR

INTERFACE

(OPTIONAL)

RAS

CAS

DQM

WE

CLK

CKE

A10

CS

SDRAM

(OPTIONAL)

ADDR

DATA

Figure 4. Shared Memory Multiprocessing System

or DMA-transferred to on-chip memory. Each link port has its

own double-buffered input and output registers. Clock/acknowl-

edge handshaking controls link port transfers. Transfers are

programmable as either transmit or receive.

Serial Ports

The ADSP-21161N features four synchronous serial ports that

provide an inexpensive interface to a wide variety of digital and

mixed-signal peripheral devices. Each serial port is made up of

two data lines, a clock and frame sync. The data lines can be

programmed to either transmit or receive.

–8–

REV. A

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