ADSP-21161NKCA-100(RevA) Ver la hoja de datos (PDF) - Analog Devices
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ADSP-21161NKCA-100 Datasheet PDF : 60 Pages
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ADSP-21161N
ADSP-21161N Family Core Architecture
The ADSP-21161N includes the following architectural features
of the ADSP-2116x family core. The ADSP-21161N is code
compatible at the assembly level with the ADSP-21160, ADSP-
21060, ADSP-21061, ADSP-21062, and ADSP-21065L.
SIMD Computational Engine
The ADSP-21161N contains two computational processing
elements that operate as a Single Instruction Multiple Data
(SIMD) engine. The processing elements are referred to as PEX
and PEY, and each contains an ALU, multiplier, shifter, and
register file. PEX is always active, and PEY may be enabled by
setting the PEYEN mode bit in the MODE1 register. When this
mode is enabled, the same instruction is executed in both pro-
cessing elements, but each processing element operates on
different data. This architecture is efficient at executing math
intensive DSP algorithms.
Entering SIMD mode also has an effect on the way data is trans-
ferred between memory and the processing elements. When in
SIMD mode, twice the data bandwidth is required to sustain
computational operation in the processing elements. Because of
this requirement, entering SIMD mode also doubles the
bandwidth between memory and the processing elements. When
using the DAGs to transfer data in SIMD mode, two data values
are transferred with each access of memory or the register file.
SIMD is supported only for internal memory accesses and is not
supported for off-chip accesses.
Independent, Parallel Computation Units
Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform single-cycle
instructions. The three units within each processing element are
arranged in parallel, maximizing computational throughput.
Single multifunction instructions execute parallel ALU and mul-
tiplier operations. In SIMD mode, the parallel ALU and
multiplier operations occur in both processing elements. These
computation units support IEEE 32-bit single-precision floating-
point, 40-bit extended precision floating-point, and 32-bit
fixed-point data formats.
Data Register File
A general-purpose data register file is contained in each process-
ing element. The register files transfer data between the
computation units and the data buses, and store intermediate
results. These 10-port, 32-register (16 primary, 16 secondary)
register files, combined with the ADSP-2116x enhanced Harvard
architecture, allow unconstrained data flow between computa-
tion units and internal memory. The registers in PEX are referred
to as R0–R15 and in PEY as S0–S15.
Single-Cycle Fetch of Instruction and Four Operands
The ADSP-21161N features an enhanced Harvard architecture
in which the data memory (DM) bus transfers data and the
program memory (PM) bus transfers both instructions and data
(see Figure 1 on Page 4). With the ADSP-21161N’s separate
program and data memory buses and on-chip instruction cache,
the processor can simultaneously fetch four operands (two over
each data bus) and an instruction (from the cache), all in a
single cycle.
Instruction Cache
The ADSP-21161N includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and four
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This cache
enables full-speed execution of core, looped operations such as
digital filter multiply-accumulates, and FFT butterfly processing.
Data Address Generators With Hardware Circular
Buffers
The ADSP-21161N’s two data address generators (DAGs) are
used for indirect addressing and implementing circular data
buffers in hardware. Circular buffers allow efficient programming
of delay lines and other data structures required in digital signal
processing, and are commonly used in digital filters and Fourier
transforms. The two DAGs of the ADSP-21161N contain suffi-
cient registers to allow the creation of up to 32 circular buffers
(16 primary register sets, 16 secondary). The DAGs automati-
cally handle address pointer wrap-around, reduce overhead,
increase performance, and simplify implementation. Circular
buffers can start and end at any memory location.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel
operations, for concise programming. For example, the ADSP-
21161N can conditionally execute a multiply, an add, and a
subtract in both processing elements, while branching, all in a
single instruction.
ADSP-21161N Memory and I/O Interface Features
The ADSP-21161N adds the following architectural features to
the ADSP-2116x family core:
Dual-Ported On-Chip Memory
The ADSP-21161N contains one megabit of on-chip SRAM,
organized as two blocks of 0.5 M bits. Each block can be config-
ured for different combinations of code and data storage. Each
memory block is dual-ported for single-cycle, independent
accesses by the core processor and I/O processor. The dual-
ported memory in combination with three separate on-chip buses
allow two data transfers from the core and one from the I/O
processor, in a single cycle. On the ADSP-21161N, the memory
can be configured as a maximum of 32K words of 32-bit data,
64K words of 16-bit data, 21K words of 48-bit instructions (or
40-bit data), or combinations of different word sizes up to one
megabit. All of the memory can be accessed as 16-bit, 32-bit,
48-bit, or 64-bit words. A 16-bit floating-point storage format is
supported that effectively doubles the amount of data that may
be stored on-chip. Conversion between the 32-bit floating-point
and 16-bit floating-point formats is done in a single instruction.
While each memory block can store combinations of code and
data, accesses are most efficient when one block stores data using
the DM bus for transfers, and the other block stores instructions
and data using the PM bus for transfers. Using the DM bus and
REV. A
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