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ADS-117

12-Bit, 2MHz, Low-Power Sampling A/D Converters

Murata Power Solutions 

FUNCTIONAL SPECIFICATIONS. CONT.

PHYSICAL/ENVIRONMENTAL

Operating Temp. Range, Case

ADS-117MC

ADS-117ME

ADS-117MM, 883

Storage Temperature Range

Thermal Impedance

θjc

θca

Package Type

Weight

0

—

+70

°C

–45

—

+85

°C

–55

—

+125

°C

–65

—

+150

°C

—

3

—

°C/W

—

23

—

°C/W

24-pin, metal-sealed, ceramic DDIP

0.42 ounces (12 grams)

TECHNICAL NOTES

1. Applications which are unaffected by endpoint errors or remove them

through software will use the typical connections shown in Figure 3.

Remove system errors or adjust the small initial errors of the ADS-117

to zero using the optional external circuitry shown in Figure 4. The

external adjustment circuit has no effect on the throughput rate.

2. Always connect the analog and digital grounds to a ground plane

beneath the converter for best performance. The analog and digital

grounds are not connected to each other internally.

3. Bypass the analog and digital supplies and the +10V reference (pin 21)

to ground with 4.7μF, 25V tantalum electrolytic capacitors in parallel

with 0.1μF ceramic capacitors. Bypass the +10V reference (pin 21) to

ANALOG GROUND (pin 23).

4. Obtain straight binary/offset binary output coding by tying COMP BIN

(pin 18) to +5V or leaving it open. The device has an internal pull-up

resistor on this pin. To obtain complementary binary or complementary

offset binary output coding, tie pin 18 to ground. The pin 18 signal

ADS-117

12-Bit, 2MHz, Low-Power Sampling A/D Converters

is compatible with CMOS/TTL logic levels for those users desiring

dynamic control of this function. Do not change COMP BIN status while

EOC is high.

5. To enable the three-state outputs, connect ENABLE (pin 17) to a logic

"0" (low). To disable, connect pin 17 to a logic "1" (high).

6. To meet the guaranteed conversion rate, a maximum start convert pulse

is specified. A wider start convert pulse will result in slower conversion

rates. An initial start convert pulse is required before performing an

actual conversion after power-up to assure the sample-hold is in the

acquisition mode.

Figure 2 shows the relationship between the various input signals. The

timing shown applies over the operating temperature range and over

the operating power supply range.

7. Re-initiating the START CONVERT (pin 16) while EOC is a logic "1" (high)

will result in a new conversion sequence.

START

CONVERT

INTERNAL S/H

EOC

N

N+1

50ns typ.,

30ns min., 60ns max.

10ns min.

25ns max.

Hold

Acquisition Time

165ns typ.

170ns max.

10ns min.

17ns max.

Conversion Time

325ns typ.

60ns max.

OUTPUT

DATA

DATA N-1 VALID

350ns min.

INVALID

DATA

150ns max.

Note: Scale is approximately 25ns per division.

35ns max.

DATA N VALID

Figure 2. ADS-117 Timing Diagram

INVALID

DATA

www.murata-ps.com

Technical enquiries email: sales@murata-ps.com, tel: +1 508 339 3000

MDA_ADS-117.B01 Page 3 of 6

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