ADS-953ME Ver la hoja de datos (PDF) - Unspecified
Número de pieza
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ADS-953ME Datasheet PDF : 6 Pages
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®
®
ADS-953
ANALOG OUTPUT
Internal Reference
Voltage
Drift
External Current
DIGITAL OUTPUTS
Logic Levels
Logic "1"
Logic "0"
Logic Loading "1"
Logic Loading "0"
Output Coding
POWER REQUIREMENTS
Power Supply Ranges
+15V Supply
–15V Supply
+5V Supply
–5V Supply
Power Supply Currents
+15V Supply
–15V Supply
+5V Supply
–5V Supply
Power Dissipation
Power Supply Rejection
MIN.
+25°C
TYP.
MAX.
0 to +70°C
MIN.
TYP. MAX.
–40 to +110°C
MIN. TYP.
MAX.
UNITS
+4.95
+5.0
+5.05
+4.95
+5.0
+5.05
+4.95
+5.0
+5.05
Volts
—
±30
—
—
±30
—
—
±30
—
ppm/°C
—
1
—
—
1
—
—
1
—
mA
+2.4
—
—
+2.4
—
—
+2.4
—
—
Volts
—
—
+0.4
—
—
+0.4
—
—
+0.4
Volts
—
—
–4
—
—
–4
—
—
–4
mA
—
—
+4
—
—
+4
—
—
+4
mA
Complementary Offset Binary
+14.5
–14.5
+4.75
–4.75
—
—
—
—
—
—
+15.0
–15.0
+5.0
–5.0
+29
–15
+104
–54
1.45
—
+15.5
–15.5
+5.25
–5.25
—
—
—
—
1.65
±0.05
+14.5
–14.5
+4.75
–4.75
—
—
—
—
—
—
+15.0
–15.0
+5.0
–5.0
+29
–15
+104
–54
1.45
—
+15.5
–15.5
+5.25
–5.25
—
—
—
—
1.65
±0.05
+14.5
–14.5
+4.75
–4.75
—
—
—
—
—
—
+15.0
–15.0
+5.0
–5.0
+29
–15
+104
–54
1.45
—
+15.5
–15.5
+5.25
–5.25
—
—
—
—
1.65
±0.05
Volts
Volts
Volts
Volts
mA
mA
mA
mA
Watts
%FSR/%V
Footnotes:
➀ All power supplies must be on before applying a start convert pulse. All supplies
and the clock (START CONVERT) must be present during warmup periods. The
device must be continuously converting during this time.
➁ Contact DATEL for other input voltage ranges.
➂ A 1MHz clock with a 500nsec positive pulse width (50% duty cycle) is used for
all production testing. Any duty cycle may be used as long as a minimum
positive pulse width of 20nsec is maintained. For applications requiring lower
sampling rates, clock frequencies lower than 1MHz may be used.
➃ Effective bits is equal to:
Full Scale Amplitude
(SNR + Distortion) – 1.76 + 20 log
Actual Input Amplitude
6.02
➄ This is the time required before the A/D output data is valid once the analog input
is back within the specified range.
TECHNICAL NOTES
1. Obtaining fully specified performance from the ADS-953
requires careful attention to pc-card layout and power
supply decoupling. The device's analog and digital ground
systems are not connected to each other internally. For
optimal performance, tie all ground pins (3, 12 and 13)
directly to a large analog ground plane beneath the pack-
age.
Bypass all power supplies and the +5V REFERENCE
OUTPUT (pin 5) to ground with 10µF tantalum capacitors in
parallel with 0.1µF ceramic capacitors. Locate the bypass
capacitors as close to the unit as possible. Tie a 47µF
capacitor between COMPENSATION (pin 7) and ground.
2. The ADS-953 achieves its specified accuracies without the
need for external calibration. If required, the device's small
initial errors can be reduced to zero using the adjustment
circuitry shown in Figure 2. When using this circuitry, or any
similar offset and gain calibration hardware, make adjust-
ments following warmup. To avoid interaction, always adjust
offset before gain. Float pin 6 if not using gain adjust
circuits.
3. Applying a start convert pulse while a conversion is in prog-
ress (EOC = logic "1") will initiate a new and probably
inaccurate conversion cycle. Data for the interrupted and
subsequent conversions will be invalid.
3
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