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ADP3164

5-Bit Programmable 4-Phase Synchronous Buck Controller

Analog Devices 

ADP3164

On each of the following cycles of the oscillator, the outputs

cycle between each of the active PWM outputs. In each case,

the current comparator resets the PWM output low when the

VT1 is reached. The current of each phase is sensed with the

same resistor and the same comparator, so the current is

inherently balanced. As the load current increases, the output

voltage starts to decrease. This causes an increase in the output

of the voltage error amplifier (gm), which in turn leads to an

increase in the current comparator threshold VT1, thus tracking

the load current.

Active Current Sharing

The ADP3164 ensures current balance in all the active phases

by sensing the current through a single sense resistor. During

one phase’s ON time, the current through the respective high

side MOSFET and inductor is measured through the sense

resistor. When the comparator threshold is reached, the high

side MOSFET turns off. On the next cycle the ADP3164

switches to the next phase. The current is measured with the

same sense resistor and the same internal comparator, ensuring

accurate matching. This scheme is immune to imbalances in the

MOSFET’s RDS(ON) and inductor parasitic resistance.

If for some reason one of the phases has a short circuit failure,

the other phases will still be limited to their maximum output

current (one over the total number phases times the total short

circuit current limit). If this is not sufficient to supply the load,

the output voltage will droop and cause the PWRGD output to

signal that the output voltage has fallen out of its specified

range. If one of the phases has an open circuit failure, the

ADP3164 will detect the open phase and signal the problem via

the PWRGD pin (see Power Good Monitoring section).

Current Sharing in Multi-VRM Applications

The ADP3164 includes a SHARE pin to allow multiple VRMs

to accurately share load current. In multiple VRM applications,

the SHARE pins should be connected together. This pin is a

low impedance buffered output of the COMP pin voltage. The

output of the buffer is internally connected to set the threshold

of the current sense comparator. The buffer has a 400 µA sink

current, and a 2 mA sourcing capability. The strong pull-up

allows one VRM to control the current threshold set point for

all ADP3164s connected together. The ADP3164’s high accu-

racy current set threshold ensures good current balance between

VRMs. Also, the low impedance of the buffer minimizes noise

pickup on this trace which is routed to multiple VRMs. This

circuit operates in addition to the active current sharing between

phases of each VRM described above.

Short Circuit Protection

The ADP3164 has multiple levels of short circuit protection to

ensure fail-safe operation. The sense resistor and the maximum

current sense threshold voltage given in the specifications set the

peak current limit.

When the load current exceeds the current limit, the excess

current discharges the output capacitor. When the output volt-

age is below the foldback threshold, VFB(LOW), the maximum

deliverable output current is cut by reducing the current sense

threshold from the current limit threshold, VCS(CL), to the fold-

back threshold, VCS(FOLD). Along with the resulting current

foldback, the oscillator frequency is reduced by a factor of five

when the output is 0 V. This further reduces the average current

in short circuit.

Power Good Monitoring

The power good comparator monitors the output voltage of the

supply via the FB pin. The PWRGD pin is an open drain output

whose high level (when connected to a pull-up resistor) indicates

that the output voltage is within the specified range of the nomi-

nal output voltage requested by the VID DAC. PWRGD will go

low if the output is outside this range.

Short circuits in a VRM power path are relatively easy to detect

in applications where multiple VRMs are connected to a com-

mon power plane. VRM power train open failures are not as

easily spotted, since the other VRMs may be able to supply

enough total current to keep the output voltage within the

power good voltage specification even when one VRM is not

functioning. The ADP3164 addresses this problem by monitor-

ing both the output voltage and the switch current to determine

the state of the PWRGD output.

The output voltage portion of the power good monitor domi-

nates; as long as the output voltage is outside the specified

window, PWRGD will remain low. If the output voltage is

within specification, a second circuit checks to make sure that

current is being delivered to the output by each phase. If no

current is detected in a phase for three consecutive cycles, it is

assumed that an open circuit exists somewhere in the power

path, and PWRGD will be pulled low.

Output Crowbar

The ADP3164 includes a crowbar comparator that senses when

the output voltage rises higher than the specified trip threshold,

VCROWBAR. This comparator overrides the control loop and sets

both PWM outputs low. The driver ICs turn off the high side

MOSFETs and turn on the low side MOSFETs, thus pulling

the output down as the reversed current builds up in the induc-

tors. If the output overvoltage is due to a short of the high side

MOSFET, this action will current-limit the input supply or blow

its fuse, protecting the microprocessor from destruction. The

crowbar comparator releases when the output drops below the

specified reset threshold, and the controller returns to normal

operation if the cause of the overvoltage failure does not persist.

Output Disable

The ADP3164 includes an output disable function that turns off

the control loop to bring the output voltage to 0 V. Because an

extra pin is not available, the disable feature is accomplished by

pulling the COMP pin to ground. When the COMP pin drops

below 0.8 V, the oscillator stops and all PWM signals are driven

low. This function does not place the part in low current shut-

down and the reference voltage is still available. The COMP

pin should be pulled down with an open drain type of output

capable of sinking at least 2 mA.

REV. 0

–7–

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