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ADP3159

4-Bit Programmable Synchronous Buck Controllers

Analog Devices 

ADP3159/ADP3179

5V

R1

10k⍀

FROM CPU

POWER

GOOD

C2

3.3V 68pF

R2

10k⍀

C15

1␮F

Q1

SUB45N03-13L

VLR1

2.5V, 2A

C1 +

100␮F

D2

MBR052LT1

D3

MBR052LT1

C6

L2

1␮F

1␮H

ADP3159/

ADP3179

1 NC U1 GND 20

2 VID0

NC 19

3 VID1

DRVH 18

4 VID2

DRVL 17

5 VID3

VCC 16

6 PWRGD LRFB2 15

7 LRFB1 LRDRV2 14

8 LRDRV1 COMP 13

9 FB

CT 12

10 CS–

CS+ 11

NC = NO CONNECT

+ C7

22␮F

Q4

SUB45N03-13L

L1

1.7␮H

Q3

SUB75N03-07

+ C8

1000␮F

+ C9

1000␮F

R12

4m⍀

1000␮Fx5

24m⍀ (EACH)

+ + ++ +

C17 C18 C19 C20 C21

R8

78.7k⍀

C11

68pF

3.3V

C16

1␮F

R11

10k⍀

C4

2.7nF

Q2

SUB45N03-13L

R7

10.5k⍀

C3

150pF

R4

220⍀

+ C5

100␮F

VLR2

1.8V,

2A

C10

R3

1nF

220⍀

5V STANDBY

12V

5V

VCC CORE

1.30V TO

2.05V

15A

Figure 3. 15 A Pentium III Application Circuit

On-board Linear Regulator Controllers

The ADP3159 and ADP3179 include two linear regulator controllers

to provide a low cost solution for generating additional supply rails.

In the ADP3159, these regulators are internally set to 2.5 V (LR1)

and 1.8 V (LR2) with ±2.5% accuracy. The ADP3179 is designed

to allow the outputs to be set externally using a resistor divider.

The output voltage is sensed by the high input impedance LRFB(x)

pin and compared to an internal fixed reference.

The LRDRV(x) pin controls the gate of an external N-channel

MOSFET resulting in a negative feedback loop. The only addi-

tional components required are a capacitor and resistor for

stability. Higher output voltages can be generated by placing

a resistor divider between the linear regulator output and its

respective LRFB pin. The maximum output load current is

determined by the size and thermal impedance of the external

power MOSFET that is placed in series with the supply and

controlled by the ADP3159.

The linear regulator controllers have been designed so that they

remain active even when the switching controller is in UVLO

mode to ensure that the output voltages of the linear regulators

will track the 3.3 V supply as required by Intel design specifica-

tions. By diode ORing the VCC input of the IC to the 5 VSB

and 12 V supplies as shown in Figure 3, the switching output

will be disabled in standby mode, but the linear regulators will

begin conducting once VCC rises above about 1 V. During

start-up the linear outputs will track the 3.3 V supply up until

they reach their respective regulation points, regardless of the

state of the 12 V supply. Once the 12 V supply has exceeded the

5 VSB supply by more than a diode drop, the controller IC

will track the 12 V supply. Once the 12 V supply has risen

above the UVLO value, the switching regulator will begin its

start-up sequence.

VID3

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

Table I. Output Voltage vs. VID Code

VID2

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

VID1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

VID0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

VOUT(NOM)

1.30 V

1.35 V

1.40 V

1.45 V

1.50 V

1.55 V

1.60 V

1.65 V

1.70 V

1.75 V

1.80 V

1.85 V

1.90 V

1.95 V

2.00 V

2.05 V

–6–

REV. A

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