ADN4666ARZ Ver la hoja de datos (PDF) - Analog Devices

Número de pieza

componentes Descripción

Fabricante

ADN4666ARZ

3V LVDS Quad CMOS Differential Line Driver

Analog Devices 

FEATURES

±8 kV ESD IEC 61000-4-2 contact discharge on receiver input pins

400 Mbps (200 MHz) switching rates

100 ps channel-to-channel skew (typical)

100 ps differential skew (typical)

3.3 ns propagation delay (maximum)

3.3 V power supply

High impedance outputs on power-down

Low power design (10 mW quiescent typical)

Interoperable with existing 5 V LVDS drivers

Accepts small swing (350 mV typical) differential

input signal levels

Supports open, short, and terminated input fail-safe

Conforms to TIA/EIA-644 LVDS standard

Industrial operating temperature range of −40°C to +85°C

Available in surface-mount SOIC package and low profile

TSSOP package

APPLICATIONS

Point-to-point data transmission

Multidrop buses

Clock distribution networks

Backplane receivers

GENERAL DESCRIPTION

The ADN4666 is a quad-channel, CMOS low voltage differential

signaling (LVDS) line receiver offering data rates of over 400 Mbps

(200 MHz) and ultralow power consumption.

The device accepts low voltage (350 mV typical) differential

input signals and converts them to a single-ended, 3 V TTL/CMOS

logic level.

The ADN4666 also offers active high and active low enable/disable

inputs (EN and EN) that control all four receivers. These inputs

3 V, LVDS, Quad CMOS

Differential Line Receiver

ADN4666

FUNCTIONAL BLOCK DIAGRAM

RIN1–

RIN1+

ADN4666

R1

R4

VCC

RIN4–

RIN4+

ROUT1

EN

ROUT4

EN

ROUT2

RIN2+

RIN2–

GND

R2

R3

Figure 1.

ROUT3

RIN3+

RIN3–

disable the receivers and switch the outputs to a high impedance

state. Consequently, the outputs of one or more ADN4666

devices can be multiplexed together to reduce the quiescent

power consumption to 10 mW typical.

The ADN4666 and its companion driver, the ADN4665, offer

a new solution to high speed, point-to-point data transmission

and offer a low power alternative to emitter-coupled logic (ECL)

or positive emitter-coupled logic (PECL).

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

Fax: 781.461.3113

©2009 Analog Devices, Inc. All rights reserved.

Share Link: