Test Circuits and Timing Diagrams
VCC
VCC
DINx
DOUTx+
RL/2
RL/2
VOS VOD
V
V
DOUTx–
Figure 2. Test Circuit for Driver VOD and VOS
SIGNAL
GENERATOR
VCC
DINx
50Ω
DOUTx+
CL
RL
DOUTx–
CL
CL INCLUDES LOAD AND TEST JIG CAPACITANCE.
Figure 3. Test Circuit for Driver Propagation Delay, Transition Time, and Maximum Operating Frequency
DINx
DOUTx–
DOUTx+
1.5V
tPLHD
0V (DIFFERENTIAL) VOD
1.5V
tPHLD
0V
3V
0V
VOH
VOL
VDIFF
80%
80%
0V
VDIFF = DOUT+ – DOUT–
0V
20%
20%
tTHL
tTHL
Figure 4. Driver Propagation Delay and Transition Time Waveforms
ADN4663
Rev. 0 | Page 5 of 12