ADP1051 Ver la hoja de datos (PDF) - Analog Devices
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ADP1051 Datasheet PDF : 108 Pages
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Data Sheet
ADP1051
Parameter
Measurement Accuracy
OTP Digital Comparator
Threshold Accuracy
Comparator Update Speed
Temperature Readings According to
Internal Linearization Scheme
Symbol Min
Typ
−0.3
−4.8
−2
−80
−0.9
−14.4
−0.5
−8
10
PG/ALT (OPEN-DRAIN) PIN
Output Low Level
VOL
CTRL PIN
Input Low Level
VIL
Input High Level
VIH
Leakage Current
SYNI/FLGI PINS
Input Low Level
VIL
Input High Level
VIH
Synchronization Range % of Internal Clock tSYNC
Period
SYNI Positive Pulse Width
SYNI Negative Pulse Width
SYNI Period Drift
Leakage Current
SDA, SCL PINS
Input Voltage Low
Input Voltage High
Output Voltage Low
Leakage Current
SERIAL BUS TIMING
Clock Operating Frequency
Glitch Immunity
Bus Free Time
Start Setup Time
Start Hold Time
VIL
VIH
VOL
tBUF
tSU;STA
tHD;STA
VDD − 0.8
VDD − 0.8
90
360
360
VDD − 0.8
−5
10
100
1.3
0.6
0.6
Max
+0.45
+7.2
+2
+80
Unit
% FSR
mV
% FSR
mV
+0.25
+4
+1.1
+17.6
% FSR
mV
% FSR
mV
ms
7
°C
5
°C
0.4 V
0.4 V
V
1.0
µA
0.4 V
V
110 %
ns
ns
280 ns
1.0
µA
0.8 V
V
0.4 V
+5
µA
400 kHz
50
ns
µs
µs
µs
Stop Setup Time
SDA Setup Time
SDA Hold Time
SCL Low Timeout
SCL Low Time
SCL High Time
SCL Low Extend Time
SCL, SDA Rise Time
SCL, SDA Fall Time
tSU;STO
0.6
tSU;DAT
100
tHD;DAT
125
300
tTIMEOUT
25
tLOW
0.6
tHIGH
0.6
tLOW;SEXT
tR
20
tF
20
µs
ns
ns
ns
35
ms
µs
µs
25
ms
300 ns
300 ns
Rev. B | Page 7 of 108
Test Conditions/Comments
2% to 20% of the input voltage range
0% to 100% of the input voltage range
Triggers OT_FAULT flag
T = 85°C with 100 kΩ||16.5 kΩ
T = 100°C with 100 kΩ||16.5 kΩ
Source current is set to 46 µA
(Register 0xFE2D = 0xE6); NTC R25 = 100 kΩ
(1%); beta = 4250 (1%); REXT = 16.5 kΩ (1%)
25°C to 100°C
100°C to 125°C
Sink current = 10 mA
External clock applied on SYNI/FLGI pin
External clock applied on SYNI/FLGI pin
Period drift between two consecutive
external clocks
Sink current = 3 mA
See Figure 2
Between stop and start conditions
Repeated start condition setup time
Hold time after (repeated) start condition;
after this period, the first clock is
generated
For readback
For write
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