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ADN2811
(Rev.:RevA)

OC-48/OC-48 FEC Clock and Data Recovery IC with Integrated Limiting Amp

Analog Devices 

ADN2811

Choosing AC-Coupling Capacitors

The choice of ac-coupling capacitors at the input (PIN, NIN)

and output (DATAOUTP, DATAOUTN) of the ADN2811

must be chosen carefully. When choosing the capacitors, the

time constant formed with the two 50 Ω resistors in the signal

path must be considered. When a large number of consecutive

identical digits (CIDs) are applied, the capacitor voltage can

drop due to baseline wander (see Figure 20), causing pattern

dependent jitter (PDJ).

For the ADN2811 to work robustly at OC-48, a minimum

capacitor of 0.1 µF to PIN/NIN and 0.1 µF on DATAOUTP/

DATAOUTN should be used. This is based on the assumption

that 1000 CIDs must be tolerated and that the PDJ should be

limited to 0.01 UI p-p.

DC-Coupled Application

The inputs to the ADN2811 can also be dc-coupled. This may

be necessary in burst mode applications where there are long

periods of CIDs and baseline wander cannot be tolerated. If the

inputs to the ADN2811 are dc-coupled, care must be taken not

to violate the input range and common-mode level requirements

of the ADN2811 (see Figures 21–23). If dc-coupling is required,

and the output levels of the TIA do not adhere to the levels

shown in Figures 22 and 23, then there will need to be level

shifting and/or an attenuator between the TIA outputs and the

ADN2811 inputs.

V1

CIN V2

PIN

ADN2811

+

50⍀

TIA

VREF LIMAMP

V1b CIN V2b

50⍀

CDR

NIN

COUT

DATAOUTP

COUT

DATAOUTN

1

2

V1

V1b

V2

V2b

VDIFF

3

4

VREF

VTH

VDIFF = V2–V2b

VTH = ADN2811 QUANTIZER THRESHOLD

NOTES

1. DURING DATA PATERNS WITH HIGH TRANSITION DENSITY, DIFFERENTIAL DC VOLTAGE AT V1 AND V2 IS ZERO.

2. WHEN THE OUTPUT OF THE TIA GOES TO CID, V1 AND V1b ARE DRIVEN TO DIFFERENT DC LEVELS. V2 AND V2b DISCHARGE TO THE V REF LEVEL, WHICH

EFFECTIVELY INTRODUCES A DIFFERENTIAL DC OFFSET ACROSS THE AC-COUPLING CAPACITORS.

3. WHEN THE BURST OF DATA STARTS AGAIN, THE DIFFERENTIAL DC OFFSET ACROSS THE AC-COUPLING CAPACITORS IS APPLIED TO THE INPUT LEVELS,

CAUSING A DC SHIFT IN THE DIFFERENTIAL INPUT. THIS SHIFT IS LARGE ENOUGH SUCH THAT ONE OF THE STATES, EITHER HIGH OR LOW DEPENDING ON

THE LEVELS OF V1 AND V1b WHEN THE TIA WENT TO CID, IS CANCELLED OUT. THE QUANTIZER WILL NOT RECOGNIZE THIS AS A VALID STATE.

4. THE DC OFFSET SLOWLY DISCHARGES UNTIL THE DIFFERENTIAL INPUT VOLTAGE EXCEEDS THE SENSITIVITY OF THE ADN2811. THE QUANTIZER WILL BE

ABLE TO RECOGNIZE BOTH HIGH AND LOW STATES AT THIS POINT.

Figure 20. Example of Baseline Wander

–14–

REV. A

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