ADN2811(RevA) Ver la hoja de datos (PDF) - Analog Devices

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ADN2811
(Rev.:RevA)

OC-48/OC-48 FEC Clock and Data Recovery IC with Integrated Limiting Amp

Analog Devices 

VCC

10␮F

0.1␮F 1nF

ADN2811

4 ؋ 100⍀

VCC

␮C

50⍀

TRANSMISSION

LINES

CLKOUTP

CLKOUTN

DATAOUTP

DATAOUTN

VCC

TIA

0.1␮F

50⍀

50⍀

RTH THRADJ

1nF

0.1␮F

VCC

VEE

VREF

PIN

NIN

CIN

VCC

SLICEP

SLICEN

VEE

LOL

␮C

XO1

19.44MHz

XO2

48 47 46 45 44 43 42 41 40 39 38 37

1

36

2

35

3

34

4

EXPOSED PAD

33

5

TIED OFF TO

32

VCC PLANE

6

WITH VIAS

31

7

30

8

29

9

28

10

1nF

0.1␮F

27

11 ADN2811

26

12

25

13 14 15 16 17 18 19 20 21 22 23 24

VCC

VCC

VEE

VEE

NC

NC

RATE

VEE

VCC

VEE

VCC

CF2

VCC

1nF

0.1␮F

␮C

1nF

0.1␮F

VCC

4.7␮F

(SEE TABLE IV FOR SPECS)

VCC

1nF

0.1␮F

Figure 17. Typical Application Circuit

VCC

100⍀ 100⍀

VCC

100⍀ 100⍀

0.1␮F

VTERM

50⍀

50⍀

ADN2811

0.1␮F 50⍀

50⍀

VTERM

VCC

TIA

ADN2811

50⍀

CIN

PIN

50⍀

CIN NIN

0.1␮F

50⍀ 50⍀

VREF

Figure 18. AC-Coupled Output Configuration

Figure 19. AC-Coupled Input Configuration

REV. A

–13–

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