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ADM3252EABCZ Datasheet PDF : 16 Pages
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ADM3252E
Data Sheet
THEORY OF OPERATION
C1
0.1µF
16V
C3
0.1µF
10V
10µF
0.1µF
C2
0.1µF
16V
C4
0.1µF
16V
ADM3252E
VCC
OSC
C1+ C1– V+ VISO
VOLTAGE
DOUBLER
C2+ C2– V–
VOLTAGE
INVERTER
RECT REG
ROUT1
TIN1
ROUT2
TIN2
DECODE
ENCODE
DECODE
ENCODE
ENCODE
DECODE
ENCODE
DECODE
R
RIN1*
T
TOUT1
R
RIN2*
T
TOUT2
GND
GNDISO
*INTERNAL 5kΩ PULL-DOWN RESISTOR ON THE RS-232 INPUTS.
Figure 15. Functional Block Diagram
The ADM3252E is a high speed, 2.5 kV, fully isolated, dual-
channel RS-232 transceiver device that operates from a single
power supply.
The internal circuitry consists of the following main sections:
• Isolation of power and data
• Charge pump voltage converter
• 3.3 V logic to EIA/TIA-232E transmitter
• EIA/TIA-232E to 3.3 V logic receiver
ISOLATION OF POWER AND DATA
The ADM3252E incorporates a dc-to-dc converter section,
which works on principles that are common to most power
supply designs. VCC power is supplied to an oscillating circuit
that switches current into a chip scale air core transformer. Power
is transferred to the secondary side where it is rectified to a high
dc voltage. The power is then linearly regulated to 3.3 V and
supplied to the secondary side data section and to the VISO pin.
Because the oscillator runs at a constant high frequency
independent of the load, excess power is internally dissipated
in the output voltage regulation process. Limited space for
transformer coils and components adds to the internal power
dissipation. This results in low power conversion efficiency.
The transmitter input (TINx) accepts TTL/CMOS input levels.
The driver input signal that is applied to the TINx pins is
referenced to logic ground (GND). It is coupled across the
isolation barrier, inverted, and then appears at the transceiver
section, referenced to isolated ground (GNDISO).
Similarly, the receiver input (RINx) accepts RS-232 signal levels
referenced to isolated ground (GNDISO). The RINx input is
inverted and coupled across the isolation barrier to appear at
the ROUTx pin, referenced to logic ground (GND).
The digital signals are transmitted across the isolation barrier
using iCoupler technology. Chip scale transformer windings
couple the digital signals magnetically from one side of the
barrier to the other. Digital inputs are encoded into waveforms
that are capable of exciting the primary transformer of the winding.
At the secondary winding, the induced waveforms are decoded
into the binary value that was originally transmitted.
3.0V TO 5.5V
10µF
0.1µF
VCC
VISO
ADM3252E V+
C3
+ 0.1µF
10V
0.1µF
10µF
CMOS OUTPUT
CMOS OUTPUT
CMOS INPUT
CMOS INPUT
ROUT1
ROUT2
TIN1
TIN2
C1+
C1–
TOUT1
TOUT2
RIN1
RIN2
+
C1
0.1µF
16V
EIA/TIA-232E OUTPUT
EIA/TIA-232E OUTPUT
EIA/TIA-232E INPUT
EIA/TIA-232E INPUT
GND
ISOLATION
BARRIER
C2+
C2–
V–
GNDISO
+
C2
0.1µF
16V
C4
+ 0.1µF
16V
Figure 16. Typical Operating Circuit
Rev. 0 | Page 10 of 16
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