ADM1033ARQZ-REEL(2012) Ver la hoja de datos (PDF) - ON Semiconductor
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ADM1033ARQZ-REEL Datasheet PDF : 35 Pages
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ADM1033
Table 4. ELECTRICAL CHARACTERISTICS (TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted.) (Note 1)
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
AGTL + INPUT (THERM)
Input High Level
−
0.75 x
−
V
REF
Input Low Level
−
−
0.4
V
SERIAL BUS TIMING (Note 4)
Clock Frequency, fSCLK
See Figure 2 for All Parameters
−
−
400
kHz
Glitch Immunity, tSW
−
50
−
ns
Bus Free Time, tBUF
1.3
−
−
ms
Start Setup Time, tSU:STA
0.6
−
−
ms
Start Hold Time, tHD:STA
0.6
−
−
ms
Stop Condition Setup Time tSU:STO
0.6
−
−
ms
SCL Low Time, tLOW
1.3
−
−
ms
SCL High Time, tHIGH
0.6
−
−
ms
SCL, SDA Rise Time, tr
−
−
1000
ns
SCL, SDA Fall Time, tf
−
−
300
ns
Data Setup Time, tSU:DAT
100
−
−
ns
Detect Clock Low Timeout, tTIMEOUT
(Note 5)
25
−
35
ms
1. Typicals are at TA = 25C and represent most likely parametric norm. Standby current typ. is measured with VCC = 3.3 V. Timing
specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.1 V for a rising edge.
2. Operation at 5.5 V is guaranteed by design, not production tested.
3. Recommend use of 100 kW pullup resistors for all open-drain outputs from the ADM1033.
4. Guaranteed by design, not production tested.
5. SMBus timeout disabled by default. See the SMBus section for more information.
SCL
SDA
tBUF
P
S
t LOW
tR
tHD; STA
tHD; DAT
tF
tHIGH
tSU; DAT
t HD; STA
tSU; STA
S
Figure 2. Serial Bus Timing Diagram
tSU; STO
P
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