ADL5371ACPZ-WP Ver la hoja de datos (PDF) - Analog Devices
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ADL5371ACPZ-WP Datasheet PDF : 20 Pages
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ADL5371
SPECIFICATIONS
VS = 5 V; TA = 25°C; LO = 0 dBm1 single-ended; baseband I/Q amplitude = 1.4 V p-p differential sine waves in quadrature with a 500 mV
dc bias; baseband I/Q frequency (fBB) = 1 MHz, LO frequency = 900 MHz, unless otherwise noted.
Table 1.
Parameter
ADL5371
Output Power, POUT
Output P1dB
Carrier Feedthrough
Sideband Suppression
Quadrature Error
I/Q Amplitude Balance
Second Harmonic
Third Harmonic
Output IP2
Output IP3
Noise Floor
GSM
LO INPUTS
LO Drive Level1
Input Return Loss
BASEBAND INPUTS
I/Q Input Bias Level
Input Bias Current
Input Offset Current
Differential Input Impedance
Bandwidth (0.1 dB)
Bandwidth (1 dB)
POWER SUPPLIES
Voltage
Supply Current
Conditions
Low frequency
High frequency
POUT − (fLO + (2 × fBB)), POUT = 6.2 dBm
POUT − (fLO + (3 × fBB)), POUT = 6.2 dBm
f1BB = 3.5 MHz, f2BB = 4.5 MHz, POUT = 1.6 dBm per tone
f1BB = 3.5 MHz, f2BB = 4.5 MHz, POUT = 1.6 dBm per tone
I/Q inputs = 0 V differential with a 500 mV common-mode bias,
20 MHz carrier offset
6 MHz carrier offset, POUT = 5 dBm, PLO = 6 dBm, LO = 940 MHz
Characterization performed at typical level
See Figure 9 for the return loss vs. frequency plot
Pin IBBP, Pin IBBN, Pin QBBP, Pin QBBN
Current sourcing from each baseband input with a bias of 500 mV dc2
Pin VPS1, Pin VPS2, Pin VPS3, Pin VPS4, and Pin VPS5
Min Typ Max Unit
500
MHz
1500
MHz
7.6
dBm
14.4
dBm
−50
dBm
−55
dBc
0.1
Degrees
−0.03
dB
−56
dBc
−50
dBc
57
dBm
27
dBm
−158.6
dBm/Hz
−158.5
dBc/Hz
−6 0
−7
+6 dBm
dB
500
mV
45
μA
0.1
μA
2900
kΩ
70
MHz
350
MHz
4.75
175
5.25 V
200 mA
1 Higher LO drive reduces noise at a 6 MHz carrier offset in GSM applications.
2 See the V-to-I Converter section for architecture information.
Rev. 0 | Page 3 of 20
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