ADF7021-V Ver la hoja de datos (PDF) - Analog Devices

Número de pieza

componentes Descripción

Fabricante

ADF7021-V

High Performance, Narrow-Band Transceiver IC

Analog Devices 

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

ADF7021-V

VCOIN 1

CREG1 2

VDD1 3

RFOUT 4

RFGND 5

RFIN 6

RFIN 7

RLNA 8

VDD4 9

RSET 10

CREG4 11

GND4 12

PIN 1

INDICATOR

ADF7021-V

TOP VIEW

(Not to Scale)

36 CLKOUT

35 TxRxCLK

34 TxRxDATA

33 SWD

32 VDD2

31 CREG2

30 ADCIN

29 GND2

28 SCLK

27 SREAD

26 SDATA

25 SLE

NOTES

1. THE EXPOSED PADDLE MUST BE CONNECTED

TO THE GROUND PLANE.

Figure 10. Pin Configuration

Table 8. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

VCOIN

Do not connect.

2

CREG1

Regulator Voltage for PA Block. Place a series 3.9 Ω resistor and a 100 nF capacitor between this pin and

ground for regulator stability and noise rejection.

3

VDD1

Voltage Supply for PA Block. Place decoupling capacitors of 0.1 μF and 100 pF as close as possible to this

pin. Tie all VDDx pins together.

4

RFOUT

The modulated signal is available at this pin. Output power levels are from −16 dBm to +13 dBm. The

output should be impedance matched to the desired load using suitable components.

5

RFGND

Ground for Output Stage of Transmitter. Tie all GND pins together.

6

RFIN

LNA Input for Receiver Section. Input matching is required between the antenna and the differential LNA

input to ensure maximum power transfer.

7

RFIN

Complementary LNA Input.

8

RLNA

External Bias Resistor for LNA. Optimum resistor is 1.1 kΩ with 5% tolerance.

9

VDD4

Voltage Supply for LNA/Mixer Block. Decouple this pin to ground with a 10 nF capacitor. Tie all VDDx pins

together.

10

RSET

External Resistor. Sets charge pump current and some internal bias currents. Use a 3.6 kΩ resistor with

5% tolerance.

11

CREG4

Regulator Voltage for LNA/Mixer Block. Place a 100 nF capacitor between this pin and ground for

regulator stability and noise rejection.

12, 19, 22 GND4

Ground for LNA/Mixer Block. Tie all GND pins together.

13 to 16

MIX_I, MIX_I,

MIX_Q, MIX_Q

Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left

unconnected.

17, 18, 20, FILT_I, FILT_I,

21

FILT_Q, FILT_Q,

Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left

unconnected.

23

TEST_A

Signal Chain Test Pin. This pin is high impedance under normal conditions and should be left unconnected.

24

CE

Chip Enable. Bringing CE low puts the ADF7021-V into complete power-down. Register values are lost

when CE is low, and the part must be reprogrammed after CE is brought high.

25

SLE

Load Enable, CMOS Input. When SLE goes high, the data stored in the shift registers is loaded into one of

the 16 latches. A latch is selected using the control bits.

26

SDATA

Serial Data Input. The serial data is loaded MSB first with the four LSBs as the control bits. This pin is a

high impedance CMOS input.

Rev. 0 | Page 15 of 60

Share Link: