ADF4157BRUZ-RL7(Rev0) Ver la hoja de datos (PDF) - Analog Devices
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ADF4157BRUZ-RL7 Datasheet PDF : 20 Pages
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ADF4157
SPECIFICATIONS
AVDD = DVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted;
dBm referred to 50 Ω.
Table 1.
Parameter
RF CHARACTERISTICS (3 V)
RF Input Frequency (RFIN)
B Version1
0.5/6.0
REFERENCE CHARACTERISTICS
REFIN Input Frequency
REFIN Input Sensitivity
REFIN Input Capacitance
REFIN Input Current
PHASE DETECTOR
Phase Detector Frequency3
CHARGE PUMP
ICP Sink/Source
High Value
Low Value
Absolute Accuracy
RSET Range
ICP Three-State Leakage Current
Matching
ICP vs. VCP
ICP vs. Temperature
LOGIC INPUTS
VINH, Input High Voltage
VINL, Input Low Voltage
IINH/IINL, Input Current
CIN, Input Capacitance
LOGIC OUTPUTS
VOH, Output High Voltage
VOH, Output High Voltage
VOL, Output Low Voltage
POWER SUPPLIES
AVDD
DVDD
VP
IDD
Low Power Sleep Mode
NOISE CHARACTERISTICS
Phase Noise Figure of Merit4
ADF4157 Phase Noise Floor5
Phase Noise Performance6
5800 MHz Output7
10/300
0.4/AVDD
0.7/AVDD
10
±100
32
5
312.5
2.5
2.7/10
1
2
2
2
1.4
0.6
±1
10
1.4
VDD – 0.4
0.4
2.7/3.3
AVDD
AVDD/5.5
29
10
−207
−137
−133
−87
Unit
GHz min/max
MHz min/max
V p-p min/max
V p-p min/max
pF max
μA max
MHz max
mA typ
μA typ
% typ
kΩ min/max
nA typ
% typ
% typ
% typ
V min
V max
μA max
pF max
V min
V min
V max
V min/V max
V min/V max
mA max
μA typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
Test Conditions/Comments
−10 dBm/0 dBm min/max. For lower frequencies, ensure slew
rate (SR) > 400 V/μs.
For f < 10 MHz, ensure slew rate > 50 V/μs.
For 10 MHz < REFIN < 250 MHz. Biased at AVDD/22.
For 250 MHz < REFIN < 300 MHz. Biased at AVDD/22.
Programmable.
With RSET = 5.1 kΩ.
With RSET = 5.1 kΩ.
Sink and source current.
0.5 V < VCP < VP – 0.5.
0.5 V < VCP < VP – 0.5.
VCP = VP/2.
Open-drain 1 kΩ pull-up to 1.8 V.
CMOS output chosen.
IOL = 500 μA.
23 mA typical.
@ 10 MHz PFD frequency.
@ 25 MHz PFD frequency.
@ VCO output.
@ 2 kHz offset, 25 MHz PFD frequency.
1 Operating temperature of B version is −40°C to +85°C.
2 AC-coupling ensures AVDD/2 bias.
3 Guaranteed by design. Sample tested to ensure compliance.
4 This figure can be used to calculate phase noise for any application. Use the formula –207 + 10log(fPFD) + 20logN to calculate in-band phase noise performance as seen
at the VCO output.
5 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value).
6 The phase noise is measured with the EVAL-ADF4157EB1Z and the Agilent E5052A phase noise system.
7 fREFIN = 100 MHz; fPFD = 25 MHz; offset frequency = 2 kHz; RFOUT = 5800.25 MHz; N = 232; loop bandwidth = 20 kHz.
Rev. 0 | Page 3 of 20
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