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ADE7880ACPZ-RL Datasheet PDF : 107 Pages
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ADE7880
Data Sheet
Parameter1, 2
PSM1 and PSM2 Modes
VDD Pin
IDD
PSM1 Mode
PSM2 Mode
PSM3 Mode
VDD Pin
IDD in PSM3 Mode
Min
Typ
2.4
5.3
0.2
2.4
1.8
1 See the Typical Performance Characteristics section.
2 See the Terminology section for a definition of the parameters.
2800
3
fL
means the whole number of the division.
Max
Unit
Test Conditions/Comments
3.7
V
5.8
mA
0.27
mA
For specified performance
3.7
V
6
μA
TIMING CHARACTERISTICS
VDD = 3.3 V ± 10%, AGND = DGND = 0 V, on-chip reference, CLKIN = 16.384 MHz, TMIN to TMAX = −40°C to +85°C. Note that dual
function pin names are referenced by the relevant function only within the timing tables and diagrams (see the Pin Configuration and
Function Descriptions section for full pin mnemonics and descriptions).
Table 2. I2C-Compatible Interface Timing Parameter
Parameter
SCL Clock Frequency
Hold Time (Repeated) Start Condition
Low Period of SCL Clock
High Period of SCL Clock
Set-Up Time for Repeated Start Condition
Data Hold Time
Data Setup Time
Rise Time of Both SDA and SCL Signals
Fall Time of Both SDA and SCL Signals
Setup Time for Stop Condition
Bus Free Time Between a Stop and Start Condition
Pulse Width of Suppressed Spikes
Symbol
fSCL
tHD;STA
tLOW
tHIGH
tSU;STA
tHD;DAT
tSU;DAT
tR
tF
tSU;STO
tBUF
tSP
Standard Mode
Min
Max
0
100
4.0
4.7
4.0
4.7
0.1
3.45
250
1000
300
4.0
4.7
N/A1
Fast Mode
Min Max Unit
0
400 kHz
0.6
μs
1.3
μs
0.6
μs
0.6
μs
0.1
0.9
μs
100
ns
20
300 ns
20
300 ns
0.6
μs
1.3
μs
50
ns
1 N/A means not applicable.
SDA
tF
tLOW
tF
SCL
tHD;STA
tHD;DAT
START
CONDITION
tSU;DAT
tF
tHD;STA
tSP
tF
tBUF
tHIGH
tSU;STA
REPEATED START
CONDITION
Figure 2. I2C-Compatible Interface Timing
tSU;STO
STOP
START
CONDITION CONDITION
Rev. C | Page 8 of 107
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