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ADE7753
(Rev.:RevA)

Single-Phase Multifunction Metering IC with di/dt Sensor Interface

Analog Devices 

Pin No.

12

13

14

15

16

17

18

19

20

Mnemonic

ZX

SAG

IRQ

CLKIN

CLKOUT

CS

SCLK

DOUT

DIN

ADE7753

Description

Voltage Waveform (Channel 2) Zero-Crossing Output. This output toggles logic high and logic low at the

zero crossing of the differential signal on Channel 2—see the Zero-Crossing Detection section.

This open-drain logic output goes active low when either no zero crossings are detected or a low voltage

threshold (Channel 2) is crossed for a specified duration—see the Line Voltage Sag Detection section.

Interrupt Request Output. This is an active low open-drain logic output. Maskable interrupts include active

energy register rollover, active energy register at half level, and arrivals of new waveform samples—see the

ADE7753 Interrupts section.

Master Clock for ADCs and Digital Signal Processing. An external clock can be provided at this logic input.

Alternatively, a parallel resonant AT crystal can be connected across CLKIN and CLKOUT to provide a clock

source for the ADE7753. The clock frequency for specified operation is 3.579545 MHz. Ceramic load

capacitors of between 22 pF and 33 pF should be used with the gate oscillator circuit. Refer to the crystal

manufacturer’s data sheet for load capacitance requirements.

A crystal can be connected across this pin and CLKIN as described for Pin 15 to provide a clock source for

the ADE7753. The CLKOUT pin can drive one CMOS load when either an external clock is supplied at CLKIN

or a crystal is being used.

Chip Select. Part of the 4-wire SPI serial interface. This active low logic input allows the ADE7753 to share

the serial bus with several other devices—see the ADE7753 Serial Interface section.

Serial Clock Input for the Synchronous Serial Interface. All serial data transfers are synchronized to this

clock—see the ADE7753 Serial Interface section. The SCLK has a Schmitt-trigger input for use with a clock

source that has a slow edge transition time, for example, opto-isolator output.

Data Output for the Serial Interface. Data is shifted out at this pin on the rising edge of SCLK. This logic

output is normally in a high impedance state unless it is driving data onto the serial data bus—see the

ADE7753 Serial Interface section.

Data Input for the Serial Interface. Data is shifted in at this pin on the falling edge of SCLK—see the

ADE7753 Serial Interface section.

Rev. A | Page 9 of 60

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