ADE7753(RevA) Ver la hoja de datos (PDF) - Analog Devices
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ADE7753 Datasheet PDF : 60 Pages
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ADE7753
TIMING CHARACTERISTICS
AVDD = DVDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 3.579545 MHz XTAL, TMIN to TMAX = –40°C to +85°C.
Table 2.
Parameter1, 2
Spec
Unit
Write Timing
Test Conditions/Comments
t1
50
ns (min)
CS falling edge to first SCLK falling edge.
t2
50
ns (min)
SCLK logic high pulse width.
t3
50
ns (min)
SCLK logic low pulse width.
t4
10
ns (min)
Valid data setup time before falling edge of SCLK.
t5
5
ns (min)
Data hold time after SCLK falling edge.
t6
400
ns (min)
Minimum time between the end of data byte transfers.
t7
50
ns (min)
Minimum time between byte transfers during a serial write.
t8
100
ns (min)
CS hold time after SCLK falling edge.
Read Timing
t93
4
µs (min)
Minimum time between read command (i.e., a write to
communication register) and data read.
t10
50
ns (min)
Minimum time between data byte transfers during a multibyte read.
t11
30
ns (min)
Data access time after SCLK rising edge following a write to the
communications register.
t124
100
ns (max)
Bus relinquish time after falling edge of SCLK.
10
ns (min)
t135
100
ns (max)
Bus relinquish time after rising edge of CS.
10
ns (min)
___________________________________
1 Sample tested during initial release and after any redesign or process change that could affect this parameter. All input signals are specified with tr = tf = 5 ns
(10% to 90%) and timed from a voltage level of 1.6 V.
2 See Figure 3, Figure 4, and the ADE7753 Serial Interface section.
3 Minimum time between read command and data read for all registers except waveform register, which is t9 = 500 ns min.
4 Measured with the load circuit in Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V.
5 Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish time of
the part and is independent of the bus loading.
t8
CS
SCLK
DIN
t1
1
t3
t7
t2
t4
t5
0 A5 A4 A3 A2 A1 A0
DB7
t6
t7
DB0
DB7
DB0
COMMAND BYTE
MOST SIGNIFICANT BYTE
Figure 3. Serial Write Timing
LEAST SIGNIFICANT BYTE
02875-0-081
CS
t1
SCLK
t13
t9
t10
DIN
DOUT
0
0 A5 A4 A3 A2 A1 A0
t11
COMMAND BYTE
DB7
t11
DB0
MOST SIGNIFICANT BYTE
Figure 4. Serial Read Timing
DB7
t12
DB0
LEAST SIGNIFICANT BYTE
02875-0-083
Rev. A | Page 5 of 60
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